EP3SL50 Datasheet, PDF (337/341 Pages) Altera Corporation – Stratix III Device Handbook, Volume 2

Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
Glossary
1–327
Table 1.
Glossary Table (Part 2 of 4)
Letter
J
Subject
J
Definitions
High-Speed I/O Block: Deserialization factor (width of parallel data bus).
JTAG Timing Specifications are in the following figure:
TMS
JTAG Timing
Specifications
TDI
TCK
TDO
t_JCH
t_JCP
t_JCL
t_JPZX
t_JPSU
t_JPCO
t_JPH
t_JPXZ
K
—
—
L
—
—
M
—
—
N
—
—
O
—
—
P
The block diagram shown in the following figure highlights the PLL Specification parameters:
Diagram of PLL Specifications (1)
PLL
Specifications
CLK
Core Clock
Switchover
fIN
fINPFD
N
PFD
CP
LF
VCO ^fVCO
CLKOUT Pins
fOUT_EXT
Counters
C0..C9
fOUT
GCLK
RCLK
Key
Reconfigurable in User Mode
M
External Feedback
Note:
(1) CoreClock can only be fed by dedicated clock input pins or PLL outputs.
Q
—
—
R
R_L
Receiver differential input discrete resistor (external to Stratix III device).
© July 2010 Altera Corporation
Stratix III Device Handbook, Volume 2