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EP3SL50 Datasheet, PDF (319/341 Pages) Altera Corporation – Stratix III Device Handbook, Volume 2 | |||
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Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
I/O Timing
1â309
Table 1â139 and Table 1â140 list the EP3SE260 regional clock (RCLK) adder values
that must be added to the GCLK values. Use these adder values to determine I/O
timing when the I/O pin is driven using the regional clock. This applies to all I/O
standards supported by Stratix III devices.
Table 1â139 lists the EP3SE260 column pin delay adders when using the regional
clock.
Table 1â139. EP3SE260 Column Pin Delay Adders for Regional Clock
Parameter
RCLK input adder
RCLK PLL input adder
RCLK output adder
RCLK PLL output adder
Fast Model
Industrial Commercial
0.233
-0.036
-0.204
1.899
0.311
0.028
-0.237
1.965
C2
C3
C4
C4L
I3
VCCL=
1.1 V
VCCL=
1.1 V
VCCL=
1.1 V
VCCL=
1.1 V
VCCL=
0.9 V
VCCL=
1.1 V
0.488 0.489 0.45 0.439 0.515 0.416
0.059 0.06 0.113 0.11 -0.005 -0.038
-0.334 -0.331 -0.413 -0.405 -0.44 -0.32
3.193 3.323 3.677 3.512 3.802 3.346
I4
VCCL=
1.1 V
0.458
0.121
-0.371
3.705
I4L
VCCL=
1.1 V
VCCL=
0.9 V
Units
0.439 0.515 ns
0.11 -0.005 ns
-0.405 -0.44 ns
3.512 3.802 ns
Table 1â140 lists the EP3SE260 row pin delay adders when using the regional clock in
Stratix III devices.
Table 1â140. EP3SE260 Row Pin Delay Adders for Regional Clock
Parameter
RCLK input adder
RCLK PLL input adder
RCLK output adder
RCLK PLL output adder
Fast Model
C2
Industrial
Commercial
VCCL=
1.1 V
C3
VCCL=
1.1 V
C4
VCCL=
1.1 V
C4L
VCCL=
1.1 V
VCCL=
0.9 V
I3
VCCL=
1.1 V
I4
VCCL=
1.1 V
I4L
VCCL=
1.1 V
VCCL=
0.9 V
Units
0.244
0.293 0.438 0.412 0.471 0.427 0.577 0.421 0.452 0.427 0.577 ns
0.124
0.134 0.21 0.215 0.234 0.228 0.297 0.217 0.239 0.228 0.297 ns
-0.256
-0.289 -0.418 -0.424 -0.484 -0.438 -0.591 -0.443 -0.464 -0.438 -0.591 ns
-0.134
-0.147 -0.228 -0.233 -0.254 -0.261 -0.322 -0.236 -0.262 -0.261 -0.322 ns
© July 2010 Altera Corporation
Stratix III Device Handbook, Volume 2
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