EP3SL50 Datasheet, PDF (312/341 Pages) Altera Corporation – Stratix III Device Handbook, Volume 2

1–302
Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
I/O Timing
Table 1–136. EP3SE260 Row Pins Input Timing Parameters (Part 3 of 3)
I/O Standard
DIFFERENTIAL
2.5-V
SSTL CLASS II
Clock
Fast Model
C2
Industrial Commercial
V_CCL=
1.1 V
C3
V_CCL=
1.1 V
C4
V_CCL=
1.1 V
C4L
V_CCL=
1.1 V
V_CCL=
0.9 V
I3
V_CCL=
1.1 V
I4
V_CCL=
1.1 V
I4L
V_CCL=
1.1 V
V_CCL=
0.9 V
Units
t_su
GCLK
t_h
GCLK ^tsu
PLL _th
-1.169
1.306
1.032
-0.751
-1.249
1.402
1.038
-0.739
-1.881 -1.908 -2.071 -1.995 -2.440 -1.928 -2.086 -1.995 -2.440 ns
2.121 2.156 2.341 2.250 2.701 2.186 2.369 2.250 2.701 ns
1.829 1.945 2.171 2.052 2.073 1.954 2.182 2.052 2.073 ns
-1.348 -1.445 -1.615 -1.528 -1.532 -1.440 -1.612 -1.528 -1.532 ns
Table 1–137 lists the EP3SE260 column pins output timing parameters for differential
I/O standards.
Table 1–137. EP3SE260 Column Pins Output Timing Parameters (Part 1 of 4)
I/O Standard
LVDS_E_1R
LVDS_E_3R
MINI-
LVDS_E_1R
MINI-
LVDS_E_3R
RSDS_E_1R
RSDS_E_3R
Clock
Fast Model
Industrial Commercial
C2
V_CCL=
1.1 V
C3
V_CCL=
1.1 V
C4
V_CCL=
1.1 V
C4L
V_CCL= V_CCL=
1.1 V 0.9 V
I3
V_CCL=
1.1 V
I4
V_CCL=
1.1 V
I4L
V_CCL= V_CCL=
1.1 V 0.9 V
Units
GCLK t_co
—
GCLK
PLL
t_co
3.479
3.475
3.750
3.753
5.506 5.712 6.270 6.106 6.513 5.854 6.411 6.106 6.513 ns
5.553 5.767 6.332 6.168 6.575 5.913 6.477 6.168 6.575 ns
GCLK t_co
—
GCLK
PLL
t_co
3.479
3.475
3.750
3.753
5.506 5.712 6.270 6.106 6.513 5.854 6.411 6.106 6.513 ns
5.553 5.767 6.332 6.168 6.575 5.913 6.477 6.168 6.575 ns
GCLK t_co
—
GCLK
PLL
t_co
3.479
3.475
3.750
3.753
5.506 5.712 6.270 6.106 6.513 5.854 6.411 6.106 6.513 ns
5.553 5.767 6.332 6.168 6.575 5.913 6.477 6.168 6.575 ns
GCLK t_co
—
GCLK
PLL
t_co
3.506
3.496
3.783
3.773
5.577 5.790 6.354 6.190 6.597 5.934 6.497 6.190 6.597 ns
5.567 5.779 6.344 6.180 6.587 5.923 6.487 6.180 6.587 ns
GCLK t_co
—
GCLK
PLL
t_co
3.496
3.489
3.773
3.767
5.570 5.783 6.348 6.184 6.591 5.928 6.492 6.184 6.591 ns
5.563 5.777 6.342 6.178 6.585 5.921 6.486 6.178 6.585 ns
GCLK t_co
—
GCLK
PLL
t_co
3.488
3.510
3.765
3.787
5.560 5.774 6.339 6.175 6.582 5.918 6.482 6.175 6.582 ns
5.581 5.794 6.358 6.194 6.601 5.938 6.502 6.194 6.601 ns
Stratix III Device Handbook, Volume 2
© July 2010 Altera Corporation