EP3SL50 Datasheet, PDF (284/341 Pages) Altera Corporation – Stratix III Device Handbook, Volume 2

1–274
Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
I/O Timing
Table 1–126. EP3SE110 Row Pins Input Timing Parameters (Part 2 of 3)
I/O Standard
DIFFERENTIAL
1.5-V
HSTL CLASS I
DIFFERENTIAL
1.5-V
HSTL CLASS II
DIFFERENTIAL
1.8-V
HSTL CLASS I
DIFFERENTIAL
1.8-V
HSTL CLASS II
DIFFERENTIAL
1.5-V
SSTL CLASS I
DIFFERENTIAL
1.5-V
SSTL CLASS II
DIFFERENTIAL
1.8-V
SSTL CLASS I
DIFFERENTIAL
1.8-V
SSTL CLASS II
DIFFERENTIAL
2.5-V
SSTL CLASS I
Clock
Fast Model
C2
Industrial Commercial
V_CCL=
1.1 V
C3
V_CCL=
1.1 V
C4
V_CCL=
1.1 V
C4L
V_CCL=
1.1 V
V_CCL=
0.9 V
I3
V_CCL=
1.1 V
I4
V_CCL=
1.1 V
I4L
V_CCL=
1.1 V
V_CCL=
0.9 V
Units
GCLK ^tsu
t_h
GCLK ^tsu
PLL _th
GCLK ^tsu
t_h
GCLK ^tsu
PLL _th
GCLK ^tsu
t_h
GCLK ^tsu
PLL _th
GCLK t_su
t_h
GCLK
PLL ^tsu
-0.758
0.884
1.147
-0.884
-0.758
0.884
1.147
-0.884
-0.772
0.898
1.133
-0.870
-0.772
0.898
1.133
-0.806
0.948
1.162
-0.882
-0.806
0.948
1.162
-0.882
-0.818
0.960
1.150
-0.870
-0.818
0.960
1.150
-1.154 -1.254 -1.359 -1.307 -1.649 -1.255 -1.360 -1.309 -1.693 ns
1.354 1.478 1.603 1.540 1.883 1.488 1.613 1.551 1.928 ns
1.855 2.094 2.328 2.208 2.147 2.111 2.346 2.224 2.194 ns
-1.438 -1.629 -1.812 -1.720 -1.650 -1.635 -1.818 -1.725 -1.693 ns
-1.154 -1.254 -1.359 -1.307 -1.649 -1.255 -1.360 -1.309 -1.693 ns
1.354 1.478 1.603 1.540 1.883 1.488 1.613 1.551 1.928 ns
1.855 2.094 2.328 2.208 2.147 2.111 2.346 2.224 2.194 ns
-1.438 -1.629 -1.812 -1.720 -1.650 -1.635 -1.818 -1.725 -1.693 ns
-1.163 -1.264 -1.377 -1.325 -1.667 -1.266 -1.377 -1.326 -1.710 ns
1.364 1.488 1.621 1.558 1.901 1.499 1.630 1.568 1.945 ns
1.842 2.084 2.310 2.190 2.129 2.100 2.329 2.207 2.177 ns
-1.426 -1.619 -1.794 -1.702 -1.632 -1.624 -1.801 -1.708 -1.676 ns
-1.163 -1.264 -1.377 -1.325 -1.667 -1.266 -1.377 -1.326 -1.710 ns
1.364 1.488 1.621 1.558 1.901 1.499 1.630 1.568 1.945 ns
1.842 2.084 2.310 2.190 2.129 2.100 2.329 2.207 2.177 ns
t_h
GCLK ^tsu
t_h
GCLK ^tsu
PLL _th
GCLK ^tsu
t_h
GCLK ^tsu
PLL _th
GCLK ^tsu
t_h
GCLK ^tsu
PLL _th
GCLK ^tsu
t_h
GCLK ^tsu
PLL _th
GCLK ^tsu
t_h
GCLK ^tsu
PLL _th
-0.870
-0.758
0.884
1.147
-0.884
-0.758
0.884
1.147
-0.884
-0.772
0.898
1.133
-0.870
-0.772
0.898
1.133
-0.870
-0.781
0.907
1.124
-0.861
-0.870
-0.806
0.948
1.162
-0.882
-0.806
0.948
1.162
-0.882
-0.818
0.960
1.150
-0.870
-0.818
0.960
1.150
-0.870
-0.827
0.969
1.141
-0.861
-1.426 -1.619 -1.794 -1.702 -1.632 -1.624 -1.801 -1.708 -1.676 ns
-1.154 -1.254 -1.359 -1.307 -1.649 -1.255 -1.360 -1.309 -1.693 ns
1.354 1.478 1.603 1.540 1.883 1.488 1.613 1.551 1.928 ns
1.855 2.094 2.328 2.208 2.147 2.111 2.346 2.224 2.194 ns
-1.438 -1.629 -1.812 -1.720 -1.650 -1.635 -1.818 -1.725 -1.693 ns
-1.154 -1.254 -1.359 -1.307 -1.649 -1.255 -1.360 -1.309 -1.693 ns
1.354 1.478 1.603 1.540 1.883 1.488 1.613 1.551 1.928 ns
1.855 2.094 2.328 2.208 2.147 2.111 2.346 2.224 2.194 ns
-1.438 -1.629 -1.812 -1.720 -1.650 -1.635 -1.818 -1.725 -1.693 ns
-1.163 -1.264 -1.377 -1.325 -1.667 -1.266 -1.377 -1.326 -1.710 ns
1.364 1.488 1.621 1.558 1.901 1.499 1.630 1.568 1.945 ns
1.842 2.084 2.310 2.190 2.129 2.100 2.329 2.207 2.177 ns
-1.426 -1.619 -1.794 -1.702 -1.632 -1.624 -1.801 -1.708 -1.676 ns
-1.163 -1.264 -1.377 -1.325 -1.667 -1.266 -1.377 -1.326 -1.710 ns
1.364 1.488 1.621 1.558 1.901 1.499 1.630 1.568 1.945 ns
1.842 2.084 2.310 2.190 2.129 2.100 2.329 2.207 2.177 ns
-1.426 -1.619 -1.794 -1.702 -1.632 -1.624 -1.801 -1.708 -1.676 ns
-1.178 -1.275 -1.384 -1.333 -1.673 -1.273 -1.378 -1.329 -1.712 ns
1.379 1.502 1.631 1.568 1.912 1.509 1.636 1.573 1.952 ns
1.827 2.068 2.299 2.178 2.118 2.089 2.323 2.199 2.170 ns
-1.411 -1.601 -1.780 -1.688 -1.617 -1.610 -1.792 -1.699 -1.665 ns
Stratix III Device Handbook, Volume 2
© July 2010 Altera Corporation