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EP3SL50 Datasheet, PDF (25/341 Pages) Altera Corporation – Stratix III Device Handbook, Volume 2 | |||
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Table 1â20. PLL Specifications for Stratix III Devices (Part 2 of 3)
C2
C3, I3
C4, I4
C4L, I4L
Symbol
fCLBW
tPLL_PSERR
tARESET
tINCCJ (3), (4)
tOUTPJ_DC (5)
t (5) OUTCCJ_DC
tOUTPJ_IO (5), (8)
Parameter
PLL closed-loop low bandwidth
PLL closed-loop medium
bandwidth
PLL closed-loop high bandwidth
(6)
Accuracy of PLL phase shift
Minimum pulse width on areset
signal
Input clock cycle to cycle jitter
(FREF ï³ 100 MHz)
Input clock cycle to cycle jitter
(FREF < 100 MHz)
Period Jitter for dedicated clock
output (FOUT ï³ï 100 MHz)
Period Jitter for dedicated clock
output (FOUT < 100 MHz)
Cycle to Cycle Jitter for dedicated
clock output
(FOUT ï³ï 100 MHz)
Cycle to Cycle Jitter for dedicated
clock output
(FOUT < 100 MHz)
Period Jitter for clock output on
regular IO (FOUT ï³ 100 MHz)
Period Jitter for clock output on
regular IO (FOUT < 100 MHz)
VCCL = 1.1 V
VCCL = 1.1 V
VCCL = 1.1 V
VCCL = 1.1 V
VCCL = 0.9 V
Unit
Min Typ Max Min Typ Max Min Typ Max Min Typ Max Min Typ Max
â 0.3 â â 0.3 â â 0.3 â â 0.3 â â 0.3 â MHz
â 1.5 â â 1.5 â â 1.5 â â 1.5 â â 1.5 â MHz
â 4 â â 4 â â 4 â â 4 â â 4 â MHz
â â ±50 â â ±50 â â ±50 â â ±50 â â ±50 ps
10 â â 10 â â 10 â â 10 â â 10 â â ns
â â 0.15 â â 0.15 â â 0.15 â â 0.15 â â 0.1 UI (p-p)
â â ±750 â â ±750 â â ±750 â â ±750 â â ±500 ps (p-p)
â â 175 â â 175 â â 175 â â 175 â â 225 ps (p-p)
â
â 17.5 â
â 17.5 â
â 17.5 â
â 17.5 â
â
22.5
mUI
(p-p)
â â 175 â â 175 â â 175 â â 175 â â 225 ps (p-p)
â
â 17.5 â
â 17.5 â
â 17.5 â
â 17.5 â
â
22.5
mUI
(p-p)
â â 600 â â 600 â â 600 â â 600 â â 750 ps (p-p)
â
â
60
â
â
60
â
â
60
â
â
60
â
â
75
mUI
(p-p)
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