EP3SL50 Datasheet, PDF (182/341 Pages) Altera Corporation – Stratix III Device Handbook, Volume 2

1–172
Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
I/O Timing
Table 1–88. EP3SL200 Row Pins Output Timing Parameters (Part 2 of 3)
I/O Standard
DIFFERENTIAL
1.5-V
HSTL CLASS I
DIFFERENTIAL
1.8-V
HSTL CLASS I
DIFFERENTIAL
1.5-V
SSTL CLASS I
Clock
Fast Model
C2
Industrial Commercial
V_CCL=
1.1 V
C3
V_CCL=
1.1 V
C4
V_CCL=
1.1 V
C4L
V_CCL= V_CCL=
1.1 V 0.9 V
I3
V_CCL=
1.1 V
I4
V_CCL=
1.1 V
I4L
V_CCL= V_CCL=
1.1 V 0.9 V
Units
GCLK t_co
4mA _GCLK
PLL ^tco
3.581
3.566
3.866
3.851
5.700 5.916 6.490 6.323 6.702 6.068 6.644 6.323 6.702 ns
5.686 5.901 6.475 6.308 6.687 6.053 6.629 6.308 6.687 ns
GCLK t_co
6mA _GCLK
PLL ^tco
3.555
3.535
3.840
3.820
5.681 5.898 6.472 6.305 6.684 6.050 6.627 6.305 6.684 ns
5.658 5.874 6.449 6.282 6.661 6.027 6.603 6.282 6.661 ns
GCLK t_co
8mA _GCLK
PLL ^tco
3.532
3.537
3.816
3.820
5.654 5.871 6.445 6.278 6.657 6.023 6.600 6.278 6.657 ns
5.645 5.859 6.431 6.264 6.643 6.010 6.584 6.264 6.643 ns
GCLK t_co
4mA _GCLK
PLL ^tco
3.530
3.568
3.813
3.852
5.644 5.860 6.434 6.267 6.646 6.013 6.589 6.267 6.646 ns
5.682 5.897 6.470 6.303 6.682 6.049 6.624 6.303 6.682 ns
GCLK t_co
6mA _GCLK
PLL ^tco
3.550
3.536
3.835
3.819
5.667 5.882 6.455 6.288 6.667 6.034 6.609 6.288 6.667 ns
5.644 5.858 6.430 6.263 6.642 6.010 6.584 6.263 6.642 ns
GCLK t_co
8mA _GCLK
PLL ^tco
3.152
3.536
3.376
3.812
4.936 5.115 5.637 5.478 5.865 5.239 5.762 5.478 5.865 ns
5.604 5.814 6.381 6.214 6.593 5.962 6.531 6.214 6.593 ns
GCLK t_co
10mA _GCLK
PLL ^tco
3.518
3.152
3.802
3.376
5.642 5.860 6.435 6.268 6.647 6.013 6.592 6.268 6.647 ns
4.936 5.115 5.637 5.478 5.865 5.239 5.762 5.478 5.865 ns
GCLK t_co
12mA _GCLK
PLL ^tco
3.536
3.518
3.812
3.802
5.604 5.814 6.381 6.214 6.593 5.962 6.531 6.214 6.593 ns
5.642 5.860 6.435 6.268 6.647 6.013 6.592 6.268 6.647 ns
GCLK t_co
16mA _GCLK
PLL ^tco
3.152
3.536
3.376
3.812
4.936 5.115 5.637 5.478 5.865 5.239 5.762 5.478 5.865 ns
5.604 5.814 6.381 6.214 6.593 5.962 6.531 6.214 6.593 ns
GCLK t_co
4mA _GCLK
PLL ^tco
3.518
3.562
3.802
3.845
5.642 5.860 6.435 6.268 6.647 6.013 6.592 6.268 6.647 ns
5.678 5.894 6.468 6.301 6.680 6.046 6.621 6.301 6.680 ns
GCLK t_co
6mA _GCLK
PLL ^tco
3.548
3.544
3.831
3.827
5.665 5.881 6.455 6.288 6.667 6.032 6.608 6.288 6.667 ns
5.663 5.881 6.456 6.289 6.668 6.032 6.610 6.289 6.668 ns
GCLK t_co
8mA _GCLK
PLL ^tco
3.560
3.549
3.842
3.832
5.664 5.878 6.450 6.283 6.662 6.029 6.603 6.283 6.662 ns
5.660 5.874 6.447 6.280 6.659 6.026 6.600 6.280 6.659 ns
Stratix III Device Handbook, Volume 2
© July 2010 Altera Corporation