EP3SL50 Datasheet, PDF (16/341 Pages) Altera Corporation – Stratix III Device Handbook, Volume 2

1–6
Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
Electrical Characteristics
Table 1–6. Bus Hold Parameters for Stratix III Devices (Part 2 of 2)
V_CCIO
Parameter Symbol Conditions
1.2 V
1.5 V
1.8 V
2.5 V 3.0 V/3.3 V Unit
High overdrive
current
Bus-hold trip
point
Min Max Min Max Min Max Min Max Min Max
I_ODH
0V <V_IN <V_CCIO — -120 — -160 — -200 — -300 — -500 µA
V_TRIP
—
0.45 0.95 0.50 1.00 0.68 1.07 0.70 1.70 0.80 2.00 V
On-Chip Termination (OCT) Specifications
If you enable OCT calibration, calibration is automatically performed at power-up for
the I/Os connected to the calibration block. Table 1–7 lists the Stratix III OCT
calibration block accuracy specifications.
Table 1–7. On-Chip Termination Calibration Accuracy Specifications for Stratix III Devices (Note 1)
Symbol
Description
Conditions
Calibration
Accuracy
Unit
C2
C3, C4,
I3 I4
25- R_S (2)
3.3, 3.0, 2.5, 1.8, 1.5, 1.2
Internal series termination with V_CCIO =
calibration (25- setting)
3.3, 3.0, 2.5, 1.8, 1.5, 1.2 V
±8 ±8 ±8 %
50- R_S
3.3, 3.0, 2.5, 1.8, 1.5, 1.2
Internal series termination with V_CCIO =
calibration (50- setting)
3.3, 3.0, 2.5, 1.8, 1.5, 1.2 V
±8 ±8 ±8 %
50- R_T 2.5, 1.8, 1.5, 1.2
Internal parallel termination with
calibration (50- setting)
V_CCIO = 2.5, 1.8, 1.5, 1.2 V
±10 ±10 ±10 %
20-R_S to 60-R_S
3.3, 3.0, 2.5, 1.8, 1.5, 1.2
Expanded range for internal
series termination with
calibration
(Between 20- to 60-setting)
V_CCIO =
3.3, 3.0, 2.5, 1.8, 1.5, 1.2 V
(3)
±10 ±10 ±10
%
25- R_{S _left_shift}
R_{OCT_CAL}
Internal left shift series
termination with calibration
(25- R_{S _left_shift} setting)
V_CCIO =
3.3, 3.0, 2.5, 1.8, 1.5, 1.2 V
±10 ±10 ±10 %
Internal series termination with
calibration
(4)
Notes to Table 1–7:
(1) OCT calibration accuracy is valid at the time of calibration only.
(2) 25- R_S not supported for 1.5 V and 1.2 V in Row I/O.
(3) 1.5 V and 1.2 V only supports 40- to 60- expanded range.
(4) For resistance tolerance after power-up calibration, refer to Equation 1–1 and Table 1–9 on page 1–8.
Stratix III Device Handbook, Volume 2
© July 2010 Altera Corporation