EP3SL50 Datasheet, PDF (331/341 Pages) Altera Corporation – Stratix III Device Handbook, Volume 2

Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
I/O Timing
1–321
EP3SE80 Clock Timing Parameters
Table 1–184 and Table 1–185 list the global clock timing parameters for EP3SE80
devices.
Table 1–184. EP3SE80 Column Pin Global Clock Timing Specifications
Parameter
t_CIN
t_COUT
t_PLLCIN
t_PLLCOUT
Fast Model
C2
Industrial
Commercial
V_CCL=
1.1 V
C3
V_CCL=
1.1 V
C4
V_CCL=
1.1 V
C4L
V_CCL=
1.1 V
V_CCL=
0.9 V
I3
V_CCL=
1.1 V
I4
V_CCL=
1.1 V
I4L
V_CCL=
1.1 V
V_CCL=
0.9 V
Units
2.037
2.059
2.879 3.127 3.524 3.430 3.989 3.127 3.524 3.430 3.989 ns
2.037
2.059
2.879 3.127 3.524 3.430 3.989 3.127 3.524 3.430 3.989 ns
-0.024
-0.007 -0.235 -0.315 -0.292 -0.199 -0.042 -0.315 -0.292 -0.199 -0.042 ns
-0.024
-0.007 -0.235 -0.315 -0.292 -0.199 -0.042 -0.315 -0.292 -0.199 -0.042 ns
Table 1–185. EP3SE80 Row Pin Global Clock Timing Specifications
Parameter
t_CIN
t_COUT
t_PLLCIN
t_PLLCOUT
Fast Model
C2
Industrial
Commercial
V_CCL=
1.1 V
C3
V_CCL=
1.1 V
C4
V_CCL=
1.1 V
C4L
V_CCL=
1.1 V
V_CCL=
0.9 V
I3
V_CCL=
1.1 V
I4
V_CCL=
1.1 V
I4L
V_CCL=
1.1 V
V_CCL=
0.9 V
Units
1.994
2.143
2.942 3.188 3.552 3.446 3.769 3.258 3.633 3.515 3.813 ns
1.912
2.052
2.800 3.025 3.371 3.275 3.610 3.089 3.444 3.336 3.654 ns
0.020
0.086 -0.177 -0.249 -0.221 -0.171 -0.221 -0.199 -0.173 -0.121 -0.266 ns
-0.062
-0.005 -0.319 -0.412 -0.402 -0.342 -0.380 -0.369 -0.362 -0.300 -0.425 ns
Table 1–186 and Table 1–187 list the regional clock timing parameters for EP3SE80
devices.
Table 1–186. EP3SE80 Column Pin Regional Clock Timing Specifications
Parameter
t_CIN
t_COUT
t_PLLCIN
t_PLLCOUT
Fast Model
Industrial Commercial
1.828
1.828
-0.013
-0.013
1.849
1.849
0.004
0.004
C2
V_CCL=
1.1 V
2.578
2.578
-0.224
-0.224
C3
V_CCL=
1.1 V
2.811
2.811
-0.303
-0.303
C4
V_CCL=
1.1 V
3.171
3.171
-0.280
-0.280
C4L
V_CCL=
1.1 V
V_CCL=
0.9 V
3.087 3.547
3.087 3.547
-0.187 -0.030
-0.187 -0.030
I3
V_CCL=
1.1 V
2.811
2.811
-0.303
-0.303
I4
V_CCL=
1.1 V
3.171
3.171
-0.280
-0.280
I4L
V_CCL=
1.1 V
V_CCL=
0.9 V
3.087 3.547
3.087 3.547
-0.187 -0.030
-0.187 -0.030
Units
ns
ns
ns
ns
Table 1–187. EP3SE80 Row Pin Regional Clock Timing Specifications
Parameter
t_CIN
t_COUT
t_PLLCIN
t_PLLCOUT
Fast Model
Industrial Commercial
1.812
1.730
0.010
-0.072
1.928
1.837
0.087
-0.004
C2
V_CCL=
1.1 V
2.638
2.496
-0.176
-0.318
C3
V_CCL=
1.1 V
2.874
2.711
-0.259
-0.422
C4
V_CCL=
1.1 V
3.205
3.024
-0.231
-0.412
C4L
V_CCL=
1.1 V
V_CCL=
0.9 V
3.107 3.332
2.936 3.173
-0.167 -0.229
-0.338 -0.388
I3
V_CCL=
1.1 V
2.938
2.768
-0.210
-0.380
I4
V_CCL=
1.1 V
3.277
3.088
-0.169
-0.358
I4L
V_CCL=
1.1 V
V_CCL=
0.9 V
3.169 3.373
2.990 3.214
-0.118 -0.275
-0.297 -0.434
Units
ns
ns
ns
ns
© July 2010 Altera Corporation
Stratix III Device Handbook, Volume 2