EP3SL50 Datasheet, PDF (208/341 Pages) Altera Corporation – Stratix III Device Handbook, Volume 2

1–198
Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
I/O Timing
Table 1–97. EP3SL340 Column Pins Output Timing Parameters (Part 4 of 4)
I/O Standard
Clock
DIFFERENTIAL
2.5-V SSTL
CLASS I
DIFFERENTIAL
2.5-V SSTL
CLASS II
8mA
10mA
12mA
16mA
GCLK
GCLK
PLL
GCLK
GCLK
PLL
GCLK
GCLK
PLL
GCLK
GCLK
PLL
Fast Model
Industrial Commercial
C2
V_CCL=
1.1 V
C3
V_CCL=
1.1 V
C4
V_CCL=
1.1 V
C4L
V_CCL= V_CCL=
1.1 V 0.9 V
I3
V_CCL=
1.1 V
I4
V_CCL=
1.1 V
I4L
V_CCL= V_CCL=
1.1 V 0.9 V
Units
t_co 3.461
3.730 5.481 5.678 6.219 6.067 6.475 5.813 6.352 6.200 6.553 ns
t_co 1.450
1.636 2.155 2.252 2.482 2.483 2.551 2.361 2.589 2.592 2.537 ns
t_co 3.461
3.730 5.481 5.678 6.219 6.067 6.475 5.813 6.352 6.200 6.553 ns
t_co 1.450
1.636 2.155 2.252 2.482 2.483 2.551 2.361 2.589 2.592 2.537 ns
t_co 3.451
3.720 5.471 5.668 6.209 6.057 6.465 5.803 6.343 6.191 6.544 ns
t_co 1.440
1.626 2.145 2.242 2.472 2.473 2.541 2.351 2.580 2.583 2.528 ns
t_co 3.444
3.712 5.457 5.653 6.193 6.041 6.449 5.787 6.326 6.174 6.527 ns
t_co 1.433
1.618 2.131 2.227 2.456 2.457 2.525 2.335 2.563 2.566 2.511 ns
Stratix III Device Handbook, Volume 2
© July 2010 Altera Corporation