EP3SL50 Datasheet, PDF (56/341 Pages) Altera Corporation – Stratix III Device Handbook, Volume 2

1–46
Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
I/O Timing
Table 1–43. EP3SL50 Column Pins output Timing Parameters (Part 3 of 7)
I/O
Standard
Clock
Fast Model
C2
Industrial Commercial
V_CCL=
1.1 V
C3
V_CCL=
1.1 V
C4
V_CCL=
1.1 V
C4L
V_CCL= V_CCL=
1.1 V 0.9 V
I3
V_CCL=
1.1 V
I4
V_CCL=
1.1 V
I4L
V_CCL= V_CCL=
1.1 V 0.9 V
Units
GCLK t_co
2mA _GCLK
PLL ^tco
3.359
3.715
3.347
3.715
4.782 5.197 5.726 5.608 5.810 5.197 5.726 5.608 5.810 ns
5.304 5.759 6.336 6.193 6.460 5.759 6.336 6.193 6.460 ns
GCLK t_co
4mA _GCLK
PLL ^tco
3.178
3.534
3.166
3.534
4.503 4.888 5.379 5.262 5.461 4.888 5.379 5.262 5.461 ns
5.025 5.450 5.989 5.847 6.112 5.450 5.989 5.847 6.112 ns
GCLK t_co 3.096
3.084 4.396 4.773 5.268 5.150 5.352 4.773 5.268 5.150 5.352 ns
6mA _GCLK
PLL ^tco
3.452
3.452 4.918 5.335 5.878 5.735 6.002 5.335 5.878 5.735 6.002 ns
1.8 V
GCLK t_co 3.076
3.064 4.337 4.719 5.202 5.084 5.286 4.719 5.202 5.084 5.286 ns
8mA _GCLK
PLL ^tco
3.432
3.432 4.860 5.281 5.812 5.669 5.936 5.281 5.812 5.669 5.936 ns
GCLK t_co
10mA _GCLK
PLL ^tco
3.013
3.369
3.001
3.369
4.276 4.644 5.121 5.003 5.205 4.644 5.121 5.003 5.205 ns
4.799 5.206 5.731 5.588 5.855 5.206 5.731 5.588 5.855 ns
GCLK t_co
12mA _GCLK
PLL ^tco
2.995
3.351
2.983
3.351
4.256 4.623 5.098 4.980 5.182 4.623 5.098 4.980 5.182 ns
4.778 5.185 5.708 5.565 5.832 5.185 5.708 5.565 5.832 ns
GCLK t_co
2mA _GCLK
PLL ^tco
3.305
3.661
3.293
3.661
4.710 5.129 5.664 5.546 5.748 5.129 5.664 5.546 5.748 ns
5.233 5.691 6.274 6.131 6.398 5.691 6.274 6.131 6.398 ns
GCLK t_co
4mA _GCLK
PLL ^tco
3.093
3.449
3.081
3.449
4.391 4.773 5.272 5.154 5.356 4.773 5.272 5.154 5.356 ns
4.914 5.335 5.882 5.739 6.006 5.335 5.882 5.739 6.006 ns
GCLK t_co 3.068
3.056 4.324 4.713 5.205 5.087 5.289 4.713 5.205 5.087 5.289 ns
6mA _GCLK
PLL ^tco
3.424
3.424 4.847 5.275 5.815 5.672 5.939 5.275 5.815 5.672 5.939 ns
1.5 V
GCLK t_co 3.057
3.045 4.307 4.688 5.185 5.067 5.269 4.688 5.185 5.067 5.269 ns
8mA _GCLK
PLL ^tco
3.413
3.413 4.830 5.250 5.795 5.652 5.919 5.250 5.795 5.652 5.919 ns
GCLK t_co
10mA _GCLK
PLL ^tco
3.002
3.358
2.990
3.358
4.269 4.637 5.115 4.997 5.199 4.637 5.115 4.997 5.199 ns
4.792 5.199 5.725 5.582 5.849 5.199 5.725 5.582 5.849 ns
GCLK t_co
12mA _GCLK
PLL ^tco
2.997
3.353
2.985
3.353
4.253 4.626 5.104 4.986 5.188 4.626 5.104 4.986 5.188 ns
4.775 5.188 5.714 5.571 5.838 5.188 5.714 5.571 5.838 ns
Stratix III Device Handbook, Volume 2
© July 2010 Altera Corporation