EP3SL50 Datasheet, PDF (53/341 Pages) Altera Corporation – Stratix III Device Handbook, Volume 2

Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
I/O Timing
1–43
Table 1–42. EP3SL50 Row Pins Input Timing Parameters (Part 3 of 3)
I/O
Standard
Clock
Fast Model
C2
Industrial Commercial
V_CCL=
1.1 V
C3
V_CCL=
1.1 V
C4
V_CCL=
1.1 V
C4L
V_CCL=
1.1 V
V_CCL=
0.9 V
I3
V_CCL=
1.1 V
I4
V_CCL=
1.1 V
I4L
V_CCL=
1.1 V
V_CCL=
0.9 V
Units
1.2-V
HSTL
CLASS I
GCLK ^tsu
t_h
GCLK ^tsu
PLL _th
1.2-V
HSTL
CLASS II
GCLK ^tsu
t_h
GCLK ^tsu
PLL _th
GCLK ^tsu
t_h
3.0-V PCI
GCLK ^tsu
PLL _th
3.0-V
PCI-X
GCLK ^tsu
t_h
GCLK ^tsu
PLL _th
0.904
-0.655
-0.884
0.997
0.910
-0.661
-0.884
0.997
0.910
-0.661
-0.890
1.003
0.904
-0.655
-0.890
1.003
0.906
-0.645
-0.914
1.040
0.917
-0.656
-0.914
1.040
0.917
-0.656
-0.925
1.051
0.906
-0.645
-0.925
1.051
1.473 -1.503 -1.682 -1.598 -1.620 -1.497 -1.674 -1.587 -1.665 ns
1.473 -1.311 -1.418 -1.362 -1.630 -1.322 -1.428 -1.374 -1.666 ns
-1.291 -1.412 -1.634 -1.580 -1.842 -1.428 -1.639 -1.588 -1.875 ns
1.554 1.774 1.924 1.808 1.834 1.768 1.931 1.777 1.885 ns
1.476 1.619 1.864 1.796 2.057 1.645 1.878 1.814 2.090 ns
-1.291 -1.412 -1.634 -1.580 -1.842 -1.428 -1.639 -1.588 -1.875 ns
-1.291 -1.412 -1.634 -1.580 -1.842 -1.428 -1.639 -1.588 -1.875 ns
1.554 1.774 1.924 1.808 1.834 1.768 1.931 1.777 1.885 ns
1.476 1.619 1.864 1.796 2.057 1.645 1.878 1.814 2.090 ns
-1.288 -1.413 -1.637 -1.583 -1.845 -1.427 -1.644 -1.593 -1.880 ns
1.473 1.620 1.867 1.799 2.060 1.644 1.883 1.819 2.095 ns
-1.288 -1.413 -1.637 -1.583 -1.845 -1.427 -1.644 -1.593 -1.880 ns
1.557 1.773 1.921 1.805 1.831 1.769 1.926 1.772 1.880 ns
1.473 1.620 1.867 1.799 2.060 1.644 1.883 1.819 2.095 ns
1.482 1.633 1.882 1.814 2.075 1.653 1.893 1.829 2.105 ns
-1.297 -1.426 -1.652 -1.598 -1.860 -1.436 -1.654 -1.603 -1.890 ns
© July 2010 Altera Corporation
Stratix III Device Handbook, Volume 2