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EP3SL50 Datasheet, PDF (141/341 Pages) Altera Corporation – Stratix III Device Handbook, Volume 2
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Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
I/O Timing
1–131
Table 1–74 lists the EP3SL150 row pins output timing parameters for single-ended
I/O standards.
Table 1–74. EP3SL150 Row Pins Output Timing Parameters (Part 1 of 4)
I/O
Standard
Clock
3.3-V
LVTTL
4mA
8mA
GCLK tco
GCLK
PLL
tco
GCLK tco
GCLK
PLL
tco
GCLK tco
12mA
GCLK
PLL
tco
4mA
3.3-V
LVCMOS
8mA
GCLK tco
GCLK
PLL
tco
GCLK tco
GCLK
PLL
tco
3.0-V
LVTTL
4mA
8mA
GCLK tco
GCLK
PLL
tco
GCLK tco
GCLK
PLL
tco
GCLK tco
12mA
GCLK
PLL
tco
GCLK tco
3.0-V
LVCMOS
4mA
GCLK
PLL
tco
GCLK tco
8mA
GCLK
PLL
tco
4mA
GCLK tco
GCLK
PLL
tco
2.5 V
8mA
GCLK tco
GCLK
PLL
tco
GCLK tco
12mA
GCLK
PLL
tco
Fast Model
C2
Industrial
Commercial
VCCL=
1.1 V
C3
VCCL=
1.1 V
C4
VCCL=
1.1 V
C4L
VCCL= VCCL=
1.1 V 0.9 V
I3
VCCL=
1.1 V
I4
VCCL=
1.1 V
I4L
VCCL= VCCL=
1.1 V 0.9 V
Units
3.214
3.466 4.819 5.204 5.693 5.566 5.831 5.325 5.817 5.689 5.913 ns
1.420
1.606 1.985 2.065 2.256 2.277 2.285 2.167 2.360 2.380 2.277 ns
3.121
3.361 4.689 5.066 5.548 5.421 5.686 5.184 5.668 5.540 5.764 ns
1.354
1.535 1.875 1.954 2.142 2.163 2.171 2.054 2.245 2.265 2.162 ns
3.042
3.271 4.570 4.943 5.420 5.293 5.558 5.057 5.536 5.408 5.632 ns
1.275
1.446 1.769 1.854 2.046 2.067 2.075 1.955 2.145 2.165 2.062 ns
3.224
3.470 4.827 5.209 5.697 5.570 5.835 5.331 5.821 5.693 5.917 ns
1.422
1.613 1.989 2.071 2.265 2.286 2.294 2.175 2.372 2.392 2.289 ns
3.046
3.275 4.576 4.949 5.427 5.301 5.564 5.063 5.543 5.417 5.639 ns
1.279
1.450 1.780 1.869 2.056 2.077 2.085 1.967 2.154 2.174 2.071 ns
3.168
3.412 4.771 5.157 5.649 5.522 5.787 5.282 5.775 5.647 5.871 ns
1.381
1.567 1.952 2.034 2.222 2.243 2.251 2.135 2.326 2.346 2.243 ns
3.047
3.285 4.618 4.998 5.485 5.358 5.623 5.120 5.611 5.482 5.706 ns
1.280
1.455 1.815 1.892 2.077 2.098 2.106 1.993 2.181 2.200 2.097 ns
3.010
3.242 4.536 4.915 5.397 5.270 5.535 5.034 5.518 5.389 5.613 ns
1.243
1.417 1.755 1.827 2.007 2.028 2.036 1.925 2.107 2.127 2.024 ns
3.082
3.331 4.665 5.050 5.539 5.412 5.677 5.174 5.664 5.535 5.759 ns
1.302
1.479 1.850 1.927 2.113 2.134 2.142 2.026 2.217 2.236 2.133 ns
2.997
3.226 4.502 4.876 5.358 5.231 5.496 4.994 5.478 5.349 5.573 ns
1.230
1.401 1.727 1.798 1.979 2.000 2.008 1.895 2.079 2.098 1.995 ns
3.194
3.448 4.903 5.311 5.821 5.694 5.959 5.442 5.954 5.825 6.049 ns
1.407
1.604 2.060 2.160 2.367 2.388 2.396 2.267 2.478 2.498 2.395 ns
3.089
3.350 4.748 5.148 5.651 5.524 5.789 5.275 5.780 5.651 5.875 ns
1.322
1.501 1.936 2.025 2.225 2.246 2.254 2.130 2.334 2.353 2.250 ns
3.038
3.282 4.637 5.029 5.525 5.398 5.663 5.152 5.650 5.521 5.745 ns
1.265
1.457 1.852 1.939 2.134 2.155 2.163 2.041 2.239 2.259 2.156 ns
© July 2010 Altera Corporation
Stratix III Device Handbook, Volume 2
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