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EP3SL50 Datasheet, PDF (43/341 Pages) Altera Corporation – Stratix III Device Handbook, Volume 2 | |||
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Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
I/O Timing
1â33
5. Compare the results of steps 2 and 4. The increase or decrease in delay must be
added to or subtracted from the I/O Standard Output Adder delays to yield the
actual worst-case propagation delay (clock-to-output) of the PCB trace.
The Quartus II software reports the timing with the conditions listed in Table 1â37
using Equation 1â1 on page 1â7. Figure 1â6 shows the circuit that is represented by
the output timing of the Quartus II software.
Figure 1â6. Output Delay Timing Report Setup for Single-Ended Outputs and Dedicated Differential
Outputs (Note 1)
VCCIO
Output
Buffer
Output
VMEAS
VTT
RT
RS
CL
Outputp
RD
Outputn
GND
GND
Note to Figure 1â6:
(1) Output pin timing is reported at the output pin of the FPGA device. Additional delays for loading and board trace delay
must be accounted for with IBIS model simulations.
Figure 1â7 and Figure 1â8 show the circuit that is represented by the output timing of
the Quartus II software for differential outputs with single and multiple external
resistors, respectively.
Figure 1â7. Output Delay Timing Report Setup for Differential Outputs with Single External Resistor
Non-Dedicated
Differential Outputs
VMEAS
VMEAS
RP
RD
Figure 1â8. Output Delay Timing Report Setup for Differential Outputs with Three External Resistor
Non-Dedicated
Differential Outputs
VMEAS RS
RP
RD
VMEAS
RS
© July 2010 Altera Corporation
Stratix III Device Handbook, Volume 2
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