EP3SL50 Datasheet, PDF (24/341 Pages) Altera Corporation – Stratix III Device Handbook, Volume 2

Table 1–20. PLL Specifications for Stratix III Devices (Part 1 of 3)
C2
C3, I3
C4, I4
C4L, I4L
Symbol
f_IN
f_INPFD
f_VCO
t_EINDUTY
f_OUT
f_{OUT_EXT}
t_OUTDUTY
t_FCOMP
t_CONFIGPLL
t_CONFIGPHASE
f_SCANCLK
t_LOCK
t_DLOCK
Parameter
Input clock frequency
Input frequency to the PFD
PLL VCO operating range
Input clock or external feedback
clock input duty cycle
Output frequency for internal global
or regional clock
Output frequency for dedicated
external clock output
Duty cycle for external clock output
(when set to 50%)
External feedback clock
compensation time
Time required to reconfigure scan
chain
Time required to reconfigure phase
shift
scanclk frequency
Time required to lock from end of
device configuration
Time required to lock dynamically
(after switchover or reconfiguring
any non-post-scale
counters/delays)
V_CCL = 1.1 V
V_CCL = 1.1 V
V_CCL = 1.1 V
V_CCL = 1.1 V
V_CCL = 0.9 V
Unit
Min Typ Max Min Typ Max Min Typ Max Min Typ Max Min Typ Max
5
—
800
(1)
5
—
717
(1)
5
—
717
(1)
5
—
717
(1)
5
—
717
(1)
MHz
5 — 325 5 — 325 5 — 325 5 — 325 5 — 325 MHz
600 — 1600 600 — 1300 600 — 1300 600 — 1300 600 — 1300 MHz
40 — 60 40 — 60 40 — 60 40 — 60 40 — 60
%
—
—
600
(2)
—
—
500
(2)
—
—
450
(2)
—
—
450
(2)
—
—
375
(2)
MHz
—
—
800
(2)
—
—
717
(2)
—
—
717
(2)
—
—
717
(2)
—
—
717
(2)
MHz
45 50 55 45 50 55 45 50 55 45 50 55 45 50 55
%
— — 10 — — 10 — — 10 — — 10 — — 10 ns
—
3.5
—
—
3.5
—
—
3.5
—
—
3.5
—
—
3.5
—
scanclk
cycles
—
1
——
1
——
1
——
1
——
1
—
scanclk
cycles
— — 100 — — 100 — — 100 — — 100 — — 100 MHz
—— 1 —— 1 —— 1 —— 1 —— 1
ms
—— 1 —— 1 —— 1 —— 1 —— 1
ms