EP3SL50 Datasheet, PDF (191/341 Pages) Altera Corporation – Stratix III Device Handbook, Volume 2

Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
I/O Timing
1–181
Table 1–93. EP3SL340 Column Pins Output Timing Parameters (Part 2 of 7)
I/O
Standard
Clock
Fast Model
C2
Industrial Commercial
V_CCL=
1.1 V
C3
V_CCL=
1.1 V
C4
V_CCL=
1.1 V
C4L
V_CCL=
V_CCL=
1.1 V 0.9 V
I3
V_CCL=
1.1 V
I4
V_CCL=
1.1 V
I4L
V_CCL= V_CCL=
1.1 V 0.9 V
Units
GCLK t_co 3.583
4mA
GCLK
PLL ^tco
4.149
3.583
4.149
5.243 5.427 5.947 5.800 6.228 5.427 5.947 5.800 6.228 ns
6.087 6.279 6.903 6.724 7.265 6.279 6.903 6.724 7.265 ns
3.0-V
LVCMOS
GCLK t_co
8mA _GCLK
PLL ^tco
GCLK t_co
12mA _GCLK
PLL ^tco
3.504
4.070
3.499
4.063
3.504
4.070
3.499
4.063
5.120 5.298 5.812 5.665 6.093 5.298 5.812 5.665 6.093 ns
5.963 6.149 6.793 6.614 7.155 6.149 6.793 6.614 7.155 ns
5.112 5.291 5.804 5.656 6.085 5.291 5.804 5.656 6.085 ns
5.955 6.142 6.761 6.581 7.124 6.142 6.761 6.581 7.124 ns
GCLK t_co
16mA _GCLK
PLL ^tco
3.490
4.054
3.490
4.054
5.098 5.276 5.789 5.641 6.070 5.276 5.789 5.641 6.070 ns
5.940 6.126 6.767 6.588 7.129 6.126 6.767 6.588 7.129 ns
GCLK t_co 3.705
4mA
GCLK
PLL ^tco
4.269
3.705
4.269
5.450 5.654 6.194 6.047 6.475 5.654 6.194 6.047 6.475 ns
6.293 6.504 7.111 6.932 7.473 6.504 7.111 6.932 7.473 ns
GCLK t_co 3.605
3.605 5.331 5.528 6.062 5.915 6.343 5.528 6.062 5.915 6.343 ns
8mA
GCLK
PLL ^tco
4.172
4.172 6.174 6.379 6.987 6.808 7.349 6.379 6.987 6.808 7.349 ns
2.5 V
GCLK t_co 3.561
3.561 5.244 5.438 5.967 5.819 6.248 5.438 5.967 5.819 6.248 ns
12mA _GCLK
PLL ^tco
4.127
4.127 6.087 6.288 6.909 6.730 7.271 6.288 6.909 6.730 7.271 ns
GCLK t_co
16mA _GCLK
PLL ^tco
3.523
4.088
3.523
4.088
5.205 5.395 5.924 5.776 6.205 5.395 5.924 5.776 6.205 ns
6.048 6.246 6.852 6.673 7.214 6.246 6.852 6.673 7.214 ns
© July 2010 Altera Corporation
Stratix III Device Handbook, Volume 2