AMG-XB404 Datasheet, PDF (9/73 Pages) alpha microelectronics gmbh – Fully Integrated Single Motor Controller for Electrical Motors

AMG-XB404
Fully Integrated Single Motor Controller for Electrical Motors
SCLK
SCS
SDI
C[2] C[1] C[0] A[4]
A[0] R[7] R[0] P
SDO
Figure 7: Command 4, register read (32 bit)
RDY D[31]
D[0] P
5.2. IO Expander
The IO expander module serves to provide additional MCU configuration registers (see Table 2).
The address register IOEXPA is used to set the index for the configuration register accessed
through the data register IOEXPD. IOEXPD provides access to to following functions.
5.2.1. IC Revision Information
Address 0 contains the number of the current AMG-XB404 revision.
5.2.2. Test Modes, EEPROM Self-Programming Mode, Lock Indicator, Clock Control
Bit 0 of address 1 enables the digital test mode if set to 1 and cannot be read. The digital test
mode can only be left by performing an IC reset. This function is used during IC test only.
Bit 1 of address 1 sets and indicates EEPROM self-programming mode which is used to write and
read from the AMG-XB404's program EEPROM. EEPROM self-programming mode is enabled by
setting EME to 1, and left by setting EME to 0. This mode is only available when the AMG-XB404
is not locked. For details on self-programming see section 5.7.1 p. 37.
Bit 2 of address 1 indicates if the AMG-XB404 is locked, 1 indicates a locked IC, which is the initial
state. See section 5.7.1, p. 37 for the details of unlocking the IC.
Bit 3 of address 1 is reserved and must not set to 1.
Bit 4 of address 1 is used to control the output of the system clock via the CLKIO pin. When this
CLKOFF flag is set to 1 output via pin CLKIO will be disabled, e.g. when the AMG-XB404's system
clock need not be provided to off-chip circuitry. Initially CLKOFF is set to 0.
Bit 5 of address 1 is used to fix the clock select signals in the present state. When this CLKLOCK
flag is set to 1 the clock selection will be fixed according to the value present at pins CLKSEL and
XO_OSEL, see also section 5.8. page 55, i.e. noise present at these pins will not interfere with the
clock source selection. Initially CLKLOCK is set to 0.
5.2.3. Power Output Polarity and Over-Current Flag Control for DMCE
The lower nibble of address 2 controls the logic level at Power output pins. All six signal pins will
remain in high ohmic state unless DMCE0OE is set to 1. If DMCE0POL is set to 1 the connected
power stage must have an inverting input to output characteristic, otherwise the power stage must
be non-inverting.
The higher nibble of address 2 controls the power stage over-current protection interface, see also
Figure 14 on page 26. OFIPOL0 selects the polarity of the OFI signal, for an active-HIGH OFI
signal input these flags must be set to zero. OFIERR0 is set to one if an over-current error of the
associated power stage is encountered. If either flag is set the shared DMCE/PFC interrupt flag will
be set. The error flag can be reset by writing a value of 1 to OFIRES0 . Resetting the error flag is
mandatory when the shared DMCE/PFC interrupt is enabled, see also section 5.2.22 p. 14.
AMG-XB404
Revision: A
2. Nov. 2012 © All rights reserved
Page 9 of 73