AMG-XB404 Datasheet, PDF (32/73 Pages) alpha microelectronics gmbh – Fully Integrated Single Motor Controller for Electrical Motors

AMG-XB404
Fully Integrated Single Motor Controller for Electrical Motors
CNT
load
values
PFC_PWM
ENDHi
ENDH
ENDLi
ENDL
DELAY CNT
ADC_START
PFC_IAC
N
measurement
load
values
ADC
conversion
N+1
measurement
load
values
ENDHi
ENDLi
Figure 18: PFC's PWM cycle
AD-converted, rectified AC voltage, DC voltage, and rectified AC current are buffered in and can be
read from the registers VAC, VDC and IAC. As shown in figure 18 the rectified AC current is
sampled in the middle of the PFC transistor's on-period which coincides with the zero-crossing of
the PFC's reference counter. The PFC’s PWM output PFC_PWM can be inverted by setting the
PFCPOL bit in the IO port expander (see table 2 p. 14).
The PFC controller's pseudo random number generator makes use of an LFSR² capable of
producing values with a length between four and eleven bits. A new random value will be
generated each time RR is read. The random values' length is set through the RANDMAX register,
its most significant set bit determines the length of the generated value. With N denoting the
position of the most significant set bit, a pseudo random value between one and 2^{N 1}−1 is
calculated. If RANDMAX is smaller than 16 a four bit value will be generated. An optimum
feedback seed is chosen automatically for any bit width. The value returned by RR may be greater
than RANDMAX because only the most significant set bit is taken into account by the PFC
algorithm. The PFC algorithm may re-read RR if a value greater than RANDMAX is encountered.
The read/write register RC returns a 10 bit wide reference counter value which is incremented
once every DCNT clock cycles. DCNT has a width of ten bits and can be adjusted to obtain a
variable frequency ramp signal on RC. RC can usually be employed to generate a clean reference
sine value for power factor correction.
The PFC controller can signal an interrupt to the MCU by setting the LSB of the INTERRUPT
hardware port to 1. Upon interrupt execution the interrupt flag must be cleared by either the PFC's
algorithm or the MCU by setting the LSB of the INTERRUPT register to 0.
The PFC_EN hardware port is reserved for enabling and disabling power factor correction. The
2 Linear feedback shift register
AMG-XB404
Revision: A
2. Nov. 2012 © All rights reserved
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