AMG-XB404 Datasheet, PDF (19/73 Pages) alpha microelectronics gmbh – Fully Integrated Single Motor Controller for Electrical Motors

AMG-XB404
Fully Integrated Single Motor Controller for Electrical Motors
A voltage divider with an accuracy of 8 mV/bit is used to monitor the voltage at the A5V pin.
Voltage sampling is triggered by setting the VDDREQ flag within the IO expander, see section 5.2
p. 9. The VDDREQ flag will be reset to 0 when a A5V sample has been acquired. The supply
voltage can be calculated as:
A5V
=
ADC
VMON^{⋅5⋅1.8V}
1023
5.3.4. Accessing ADC Sample Data, ADC Interrupts
The ADC is configured through the ADCCONF register shown in table 6 p. 19. The ADC channel to
be addressed is chosen by setting the four least significant bits of the ADCCONF register (as
shown in detail in table 7, p. 20). By setting ADCIE to 1 ADC interrupt generation is enabled.
The interrupt flags for ADC channel 0 to 7 can be accessed through the interrupt flag register
ADCINT. To reset a specific interrupt flag the corresponding bit in the interrupt reset register
ADCIRES must be written as 1.
The two least significant bits of the conversion result are accessed through bits four and five of
ADCCONF. The eight most significant bits are held by the data register ADCD. The most significant
bit's value must always be retrieved first.
The ADC can be run in either synchronous or asynchronous mode. By setting the MSB in
ADCCONF to 0 synchronous mode is activated. In synchronous mode ADC channel 0 through 7
will only be sampled after an acquisition of the DC bus voltage to reduce distortions caused by the
IPM. In synchronous mode the sampling rate is limited to the DMCE's PWM frequency.
In asynchronous mode sampling of ADC channel 0 through 7 will be performed at the next
available time, i.e. when no ADC channel with a higher priority is pending.
Any ADC acquisition initiated by either DMCE or the PFC controller has a higher priority than ADC
channel 0 through 7. Only temperature measurements, D5V measurements and tuning cycles
have a lower priority. The pending ADC channel with the lowest number will always be sampled
first (see also Table 7).
Bit
7
6
5
4
3
Write
ASYNC
ADCIE
SEL[1:0]
0
Read
ASYNC
ADCIE
ADCD[1:0]
0
Initial value
0
0
0
0
0
Write
0
0
0
0
0
Initial value
0
0
0
0
0
Read
Initial value
0
0
0
Write
0
0
0
Initial value
0
0
0
Read
0
0
0
Initial value
0
0
0
Table 6: XB404 ADC registers
ADCD[9:2]
0
0
0
0
0
0
0
0
0
0
2
1
0
Register Comment
name
0
ADCCH[1:0]
ADC
configuration
0
ADCCH[1:0]
ADCCONF _register
0
0
0
0
IRCH[1:0]
ADC interrupt
0
0
0
ADCIRES
reset
register;
Channel 0..2
ADC data
0
0
0
ADCD
register
0
REQCH[1:0]
ADC request
0
0
0
ADCREQ register;
Channel 0..2
0
INTADCCH[1:0]
ADC interrupt
ADCINT flag register;
0
0
0
Channel 0..2
AMG-XB404
Revision: A
2. Nov. 2012 © All rights reserved
Page 19 of 73