AMG-XB404 Datasheet, PDF (11/73 Pages) alpha microelectronics gmbh – Fully Integrated Single Motor Controller for Electrical Motors

AMG-XB404
Fully Integrated Single Motor Controller for Electrical Motors
Writing DTC0RNG sets up the allowable error range for dead time compensation of DCME0. If the
actual duty cycle, determined by the feed back pins, differs from the expected duty cycle by more
than
2^{(DTC0RNG +CNT0X2)}
8
, dead time compensation will be skipped. See also section 5.2.6 on
page 10 for explanation on CNT0X2 .
5.2.9. ADC Offset Calibration Data
Addresses 14 to 25 hold the ADC offset compensation values. The order of the channels is
described in table 7 on page 20. The offset values are 8-bit signed integer numbers for positive
and negative offset-correction.
5.2.10. PFC, DMCE and ADC Software Controlled Reset Signals
Address 26 holds the reset flags for the DMCE core, the PFC controller, and the ADC interface.
The reset flags are active if set to one and initially reset to zero. Setting these flags can be used to
when units are unused.
5.2.11. Operational Amplifier Power Down Signals
Addresses 27 and 28 hold the power-down flags for all analog signal operational amplifiers. Bits 0
to 7 of address 27 control the voltage follower for ADC7 to ADC0. Bits 0 to 6 of address 28 control
the enable state of the VDC voltage follower (bit 0), VAC voltage follower (bit 1), DMCE0 current
amplifier (bit 2), , PFC current amplifier (bit 4), ADC buffer amplifier (bit 5), and reference voltage
buffer amplifier (bit 6). The MSB (bit 7) of address 28 can be used to power-down the bias supply
for all amplifiers. Disabling of the operational amplifiers is performed by setting individual flags to
one, initially all flags are set to zero.
Note that disabling the current amplifier of DMCE0 will in turn disable the three associated phase
voltage read-back comparators.
5.2.12. SPI Unit Low-Pass Filter Settings
Low-pass filtering is available for both the AMG-XB404's system SPI unit and the MCU-controlled
SPI unit. Address 29 holds the time constants for each SPI unit's input signal low pass filter. The
value stated for SPILP specifies the filter depth of the low pass filter for the system SPI as a
multiple of system clock cylces. The value stated for SPILP2 specifies the filter depth of the low
pass filter for the MCU's SPI unit. The time base of the filter is the system clock. A value of 0 for
SPILP deactivated low-pass filtering, this is the default value.
5.2.13. Assignment of Power Outputs and High Voltage Read-Back Pins
In order to accommodate any phase order with a minimum of wiring effort AMG-XB404's gate
driver outputs and high voltage feedback signals are connected to freely programmable physical IC
pins. They are assigned using addresses 30 through 35.
Address 30 contains the configuration for the three pins associated with the U-phase of DMCE0.
Bits 0 to 2 configure the high-side drive signal pin. When set to a value of 1 through 6 UH will be
assigned to one of pin M0O1 through M0O6. When set to a value of 0 the pin M0O1 is driven to a
static low state, when set to 7 the pin M0O1 will be driven to a static high state.
Bits 3 to 5 configure the low-side drive signal pin. When set to a value of 1 through 6 UL will be
assigned to one of pin M0O1 through M0O6. When set to a value of 0 the pin M0O2 is driven to a
static low state, when set to 7 the pin M0O2 will be driven to a static high state.
Bits 6 and 7 configure the output state read-back pin RU. When set to a value of 1 through 3 RU
will be assigned to one of pin M0R1 through M0R3. When set to a value of 0 no read-back pin will
be assigned.
AMG-XB404
Revision: A
2. Nov. 2012 © All rights reserved
Page 11 of 73