AMG-XB404 Datasheet, PDF (51/73 Pages) alpha microelectronics gmbh – Fully Integrated Single Motor Controller for Electrical Motors

AMG-XB404
Fully Integrated Single Motor Controller for Electrical Motors
resulting
SDA
SDA from
MASTER
SDA from
SLAVE
SCL from
MASTER
MSB
address[6:0]
Figure 34: TWI address cycle
LSB R/W ACK
As shown in figure 35 a data cycle contains eight data bits and one acknowledge bit. Data is sent
MSB first. The receiving side acknowledges the received data by pulling SDA low.
resulting
SDA
MSB
SDA from
transmitter
SDA from
receiver
SCL from
MASTER
8-Bit data
Figure 35: TWI data cycle
LSB ACK
When data is sent from master to slave the TWI slave may set STOPREG to send a non-
acknowledge after receiving the next byte from the master, thus indicating that it will receive no
more data. The slave will enter a passive state after STOPREG has been set until a start condition
is received. If data requested by the master is not ready to be sent by the slave the slave will pull
the serial clock to LOW until the data is ready. This is the only case in which the slave influences
the serial clock.
Setting RW in CONFIG_REG to 0 in master mode will send data from master to slave. If RW is set
to 1 data will be received by the master. The transmission of the data held in DATA_REG is started
by setting STARTREG to 1. The transmission will be stopped after sending any pending data by
setting STOPREG to 1. The 2 bit PRESCALER determines the serial clock speed in master mode
(see table 27).
PRESCALER[1:0] Comment
0
400 kHz serial clock
1
200 kHz serial clock
2
100 kHz serial clock
3
50 kHz serial clock
Table 27: Serial clock settings
The status register STATUS_REG is used to monitor transmissions (see table 26 p. 50). The FLAG
bit indicates a transmission error i.e. non-acknowledge. In slave mode RSTART and RSTOP are
set to 1 by the TWI upon a received start respectively stop condition and will be reset automatically
after the address cycle is done. DATAWF rises to 1 if data can be written to DATA_REG. DATAWF
will be set to 0 if data is written to DATA_REG. DATARF rises to 1 when received data can be read
from DATA_REG. DATARF will be set to 0 if data is read from DATA_REG.
The TWI’s interrupt is set when DATAWF or DATARF are set. The interrupt flag remains set until
DATA_REG is read from or written to. It may also be cleared by disabling the TWI module via the
CONFIG_REG’s TWENA bit.
AMG-XB404
Revision: A
2. Nov. 2012 © All rights reserved
Page 51 of 73