AMG-XB404 Datasheet, PDF (12/73 Pages) alpha microelectronics gmbh – Fully Integrated Single Motor Controller for Electrical Motors

AMG-XB404
Fully Integrated Single Motor Controller for Electrical Motors
Addresses 31 and 32 contain the configuration for the three pins associated with the V-phase, and
W-phase of DMCE0 respectively, assigned in analogous fashion to address 30. They control the
assignment of VH, VL, WH and WL to M0O1 through M0O6, the static logic state of pins M0O3,
M0O4, M0O5, and M0O6, and the position of the output state read-back pins RV and RW to M0R1
through M0R3.
5.2.14. DMCE and PFC Driver Signal Read-Back
Addresses 36 and 37 are used to read back the logic level at the driver outputs of both DMCE and
the PFC, this can be used for system health checking.
The MSB of both addresses switches between analog and digital read back inputs. If M0RMUX is
set to 1, analog comparators are used for reading back DMCE0 driver outputs, otherwise digital
inputs are used. The same applies for M1RMUX concerning DMCE1 output read back. The analog
and digital inputs rely in the same I/O-Pads, so switching between those does not affect pin layout
configuration.
5.2.15. Band Gap Reference Tuning Setting
Address 38 holds the four bits wide band gap reference tuning setting, VBGTUN, allowing for the
on-chip reference voltage generator to be adjusted in steps of 0.4% per LSB. The initial setting of
VBGTUN is eight, corresponding to a native reference voltage. Tuning of the reference will ensure
the correct setting of all derived regulated voltages.
5.2.16. OFI Direct Read-Back
Address 39 is used for reading the state of the M0OFI input pin, bypassing the configured polarity
and low-pass filtering settings.
5.2.17. EEPROM Direct Access
Address 40 gives access to the serial interface of the EEPROM. Bit 0 is used for serially writing
data to and reading data from the EEPROM. The serial clock signal is transmitted via bit 1.
5.2.18. MCU-Accessible Engineering Mode Enable
Bit 0 of address 41 holds the MCU-accessible engineering mode enable flag EME2. By setting
EME2 to 1 the MCU can access the EEPROM via address 40 of the IO expander. To leave the
self-programming mode EME2 is set to 0, this is the default value. This bit cannot be set by the SPI
bus master.
5.2.19. ADC TUN Mode, DMCE Value Offset Selection
Bit 0 of address 42 holds the ADC tuning mode flag, TUNMODE. When set the ADC will perform a
tune cycle with each conversion. By default TUNMODE is not set.
Bit 1 and bit 2 of address 42 must remain 0, this is the default value.
Bit 3 of address 42 holds the offset select flag, OFFSSEL, used to select the offset value of
DMCE0 when set to 1, this is the default. For details see section 5.3 p. 16.
5.2.20. ADC Sample Triggers for Test, Supply Voltage, and Temperature
Address 43 gives access to additional ADC request flags.
Bit 0, IREQ, is used to trigger sampling of the DC bus voltage, rectified AC voltage, DMCE's
current values and the PFC controller's current value. Readiness is indicated by reading this flag
as 0.
Bit 1, VDDREQ, is used to trigger sampling of 5V supply voltage. Readiness is indicated by
reading VDDREQ as 0.
AMG-XB404
Revision: A
2. Nov. 2012 © All rights reserved
Page 12 of 73