AMG-XB404 Datasheet, PDF (29/73 Pages) alpha microelectronics gmbh – Fully Integrated Single Motor Controller for Electrical Motors

AMG-XB404
Fully Integrated Single Motor Controller for Electrical Motors
5.5.1. PFC Instruction Set Description
I2
I3
I1
21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OP
A
B
C
Figure 17: PFC command format
The 15 supported commands have a uniform width of 22 bits and the format shown in figure 17.
A, B, C being register or memory locations upon which the operation OP is executed. Operations
can also use the immediate values I1, I2, and I3 which are part of the command word. Table 12
p. 29 gives an overview of each command’s function.
OP Mnemonic Operation
Clock Description
cycles
0 JMP
jump I1
1 jump to 8 bit address immediate I1
1 BRN
jump I1 if  A0 
1 jump to 8 bit address immediate I1 if register/memory A is negative
(2)
2 BRP
jump I1 if  A0 
1 jump to 8 bit address immediate I1 if register/memory A is positive
(2)
3 BRZ
jump I1 if  A=0 
1 jump to 8 bit address immediate I1 if register/memory A is zero
(2)
4 ST
C= A
1 store register/memory A in register/memory C
(2)
5 ADD
C= A B
1 add register/memory A and register B and store result in register/memory C
(2)
6 SUB
C= A− B
1 subtract register B from register/memory A and store result in
(2) register/memory C
7 DIV
ANGLE=CORD _ I :CORD _ Q
50 divide CORD_I by CORD_Q in CNT (1-15) iterations, result stored in ANGLE;
for iterations register CNT is used, begin with setting ANGLE to Zero
8 CORD
CORD
_
I
=
23167⋅sin

ANGLE
2¹⁴
⋅^π₂

CORD
_
Q=
23167⋅cos

ANGLE
2¹⁴
⋅^π₂

80 execute cordic algorithm on CORD_I, CORD_Q, etc. in CNT 1-15 iterations,
result stored in CORD_I, CORD_Q; for iterations register CNT is used
9 MUL
M =A⋅B
1 multiply two registers A, B or a memory A and a register B and store result in
(2) internal register M
10 SHMR
C=M ≫ I3
1 shift multiplier result in internal register M right by I3 bits and store result in
target memory/register C
11 SHL
C= A≪I3
1 shift register/memory A left by I3 bits and store result in register/memory C
(2)
12 SHR
C= A≫I3
1 shift register/memory A right by I3 bits and store result in register/memory C
(2)
13 STI
C = I2
1 store immediate I2 (max. 12 bit) in register/memory C
14 SYNC
wait while  PFC _ IAC == 0
1 wait for PFC_IAC impulse
Table 12: PFC instruction set (The clock cycle values in braces denote the number of clock cycles if an
SRAM value needs to be read during command execution.)
AMG-XB404
Revision: A
2. Nov. 2012 © All rights reserved
Page 29 of 73