AMG-XB404 Datasheet, PDF (48/73 Pages) alpha microelectronics gmbh – Fully Integrated Single Motor Controller for Electrical Motors

AMG-XB404
Fully Integrated Single Motor Controller for Electrical Motors
table 21 p. 47). If UARTRXPOL is set to 1, the RX line is interpreted active low, otherwise it's
interpreted active high. If UARTTXPOL is set to 1, data is sent out active low, otherwise it's sent
out active high. Active high is the default setting for both lines.
The UART has got two interrupt signals that can be enabled as shown in section 5.2.22 p. 14. An
RX interrupt is generated when a new byte is received and stored in RXB, the interrupt flag is reset
by reading the RX buffer. A TX interrupt is generated when the byte in TXB has been sent, the
interrupt flag is reset by writing to the TX buffer.
Code
BAUDRATE[2:0]
0
000
1
001
2
010
3
011
4
100
Table 22: UART baud rates
Baud rate
9600
19200
38400
57600
115200
Bit
7
6
Write
UART_EN
-
Read
UART_EN
RDY
Initial value
0
0
Write
Read
Initial value
0
0
Write
Read
Initial value
0
0
Table 23: UART registers
5
-
FERR
0
0
0
4
3
-
-
OERR
0
0
0
RXB[7:0]
RXB[7:0]
0
0
TXB[7:0]
TXB[7:0]
0
0
2
1
0
BAUDRATE[2:0]
BAUDRATE[2:0]
0
0
0
0
0
0
0
0
0
Register
name
UCSR
Comment
Status and
control
register
RXB
Receive
buffer
Transmit
TXB
buffer
5.7.4. Serial Parallel Interface (SPI)
The SPI’s IO pins are mapped to GPIO pins (see figure 29 p. 46). The SPI can be run as a master
or a slave. In master mode the MCU can communicate with one or more SPI slaves. In slave mode
an SPI master can control the SPI. There is a control and a data register which are shown in detail
in table 24.
SCLK
SCS
SDO
7/0 6/1 5/2 4/3 3/4 2/5 1/6 0/7
SDI
7/0 6/1 5/2 4/3 3/4 2/5 1/6 0/7
Figure 31: SPI timing
SPI chip select SCS and SPI clock SCLK are always driven by the master. They frame and time
the transmission. Data is transferred in blocks of up to eight bits, data is always sent out
synchronously via SDO and received via SDI using a single 8 bit shift register controlled by the
serial clock. Figures 31 and 32 show an 8 bit SPI transmission. By default SDO and SDI are
sampled on the rising edge of SCLK, sampling will take place on the falling edge of SCLK if the
clock's polarity is inverted in the GPIO register (see section 5.7.2 p. 44).
AMG-XB404
Revision: A
2. Nov. 2012 © All rights reserved
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