AMG-XB404 Datasheet, PDF (10/73 Pages) alpha microelectronics gmbh – Fully Integrated Single Motor Controller for Electrical Motors

AMG-XB404
Fully Integrated Single Motor Controller for Electrical Motors
5.2.4. Switching Controller PWM Frequency
The clock pre-scaler SWCPRE for the SMPS is set using addresses 3 and 4. The lower byte has to
be written before the high byte. For the changed value to have an effect both bytes have to be
written. The SMPS clock frequency is calculated as:
f
SWC ⁼
2⋅
f _MCU
SWCPRE1
,
1 ≤ SWCPRE ≤ 32767 .
Setting SWCPRE to 0 enables an internal RC oscillator to generate the SMPS's PWM clock. Its
typical frequency is 22kHz. This is the default on startup.
5.2.5. Polarity of the PFC Switching Signal
The LSB of address 5 sets the polarity of the PFC controller’s logic level PWM output. 0 means
active HIGH, 1 means active LOW.
5.2.6. PWM Frequency Setting for DMCE
DMCE’s PWM clock setting is controlled through a register pair C1, C2 (accessible via addresses 6
to 8). The range of C1 is 0..7 (3 bit) and the range of C2 is 0..255 (8 bit). The DMCE has got an
individual pair of registers allowing independent PWM clocks. Address 6 also holds two flags,
CNT0X2 and CNT1X2, to double the PWM base frequency of the DMCE. The PWM frequency can
be calculated as:
{^{f PWM=}
f
FPU^â‹_{213⋅}^{2288−CC21} _CC21−1

⋅2

CNTX2
f _FPU⋅₂₂₂₈₁^{−−CC22}⋅2^CNTX2
; for C21
; for C2≤1
5.2.7. FLL Configuration and Status
FLL related functions are controlled using addresses 9,10, and 12. The lower byte of the divider
setting (address 9) has to be written before the high byte (address 10). The FLL divider FLLDIV is
used to set the clock frequency of the PFC, ADC, and DMCE which can be calculated as:
f
VCO ⁼
FLLDIV 1
16⋅T _RC
, where TRC is the RC-ramp's rise time.
The MCU’s clock frequency is calculated as:
f
MCU ⁼
f
VCO
8
. On reading FLLDIV the most
recently acquired VCO frequency counter value will be returned, thus allowing to monitor the VCO
frequency directly, note that the high byte and low byte of the counter value are not guaranteed to
belong to the same VCO frequency counter value.
PREC determines the FLL's frequency step for regulating the system clock frequency. Vaild values
are 4 to 11. Larger values correspond to smaller frequency steps. PREC is increased when the
target frequency is crossed within 3 frequency adjustment steps otherwise PREC will be
decreased. The maximum value of PREC is given by the value of MPREC. Both maximum PREC
value and current PREC value can be read from address 12. MPREC may also be set, its initial
value is 10.
5.2.8. U, V, W Phase Feedback Monitor
The comparator result of the signals present at M0R1, M0R2, and M0R3 can be read back from
address 13. RU, RV, and RW are assigned according to the setting detailed in section 5.2.13..
Writing bit 3, DTC0OVR, disables hardware dead time compensation for DMCE0.
AMG-XB404
Revision: A
2. Nov. 2012 © All rights reserved
Page 10 of 73