AMG-XB404 Datasheet, PDF (62/73 Pages) alpha microelectronics gmbh – Fully Integrated Single Motor Controller for Electrical Motors

Mnemonic
Operands
Description
BRGE
k
Branch if greater or equal, signed
BRLT
k
Branch if less than zero, signed
BRHS
k
Branch if half carry flag set
BRHC
k
Branch if half carry flag cleared
BRTS
k
Branch if T flag set
BRTC
k
Branch if T flag cleared
BRVS
k
Branch if overflow flag set
BRVC
k
Branch if overflow flag cleared
BRIE
k
Branch if interrupt enabled
BRID
k
Branch if interrupt disabled
DATA TRANSFER INSTRUCTIONS
MOV
Rd, Rr
Move between registers
MOVW
Rd, Rr
Copy register word
LDI
Rd, K
Load immediate
LD
Rd, X
Load indirect
LD
Rd, X+
Load indirect and post-increment
LD
Rd, -X
Load indirect and pre-decrement
LD
Rd, Y
Load indirect
LD
Rd, Y+
Load indirect and post-increment
LD
Rd, -Y
Load indirect and pre-decrement
LDD
Rd, Y+q
Load indirect with displacement
LD
Rd, Z
Load indirect
LD
Rd, Z+
Load indirect and post-increment
LD
Rd, -Z
Load indirect and pre-decrement
LDD
Rd, Z+q
Load indirect with displacement
LDS
Rd, k
Load direct from SRAM
ST
X, Rr
Store indirect
AMG-XB404
Revision: A
AMG-XB404
Fully Integrated Single Motor Controller for Electrical Motors
Operation
If (S = 0) PC ← PC + k + 1
If (S = 1) PC ← PC + k + 1
If (H = 1) PC ← PC + k + 1
If (H = 0) PC ← PC + k + 1
If (T = 1) PC ← PC + k + 1
If (T = 0) PC ← PC + k + 1
If (V = 1) PC ← PC + k + 1
If (V = 0) PC ← PC + k + 1
If (I = 1) PC ← PC + k + 1
If (I = 0) PC ← PC + k + 1
Rd ← Rr
Rd+1:Rd ← Rr+1:Rr
Rd ← K
Rd ← (X)
Rd ← (X), X ← X + 1
X ← X - 1, Rd ← (X)
Rd ← (Y)
Rd ← (Y), Y ← Y + 1
Y ← Y - 1, Rd ← (Y)
Rd ← (Y + q)
Rd ← (Z)
Rd ← (Z), Z ← Z + 1
Z ← Z - 1, Rd ← (Z)
Rd ← (Z + q)
Rd ← (k)
(X) ← Rr
-64 ≤ k ≤ 63
-64 ≤ k ≤ 63
-64 ≤ k ≤ 63
-64 ≤ k ≤ 63
-64 ≤ k ≤ 63
-64 ≤ k ≤ 63
-64 ≤ k ≤ 63
-64 ≤ k ≤ 63
-64 ≤ k ≤ 63
-64 ≤ k ≤ 63
0 ≤ d ≤ 31; 0 ≤ r ≤ 31
d = 0, 2...30; r = 0, 2...30
16 ≤ d ≤ 31; 0 ≤ K ≤ 255
0 ≤ d ≤ 31
0 ≤ d ≤ 31
0 ≤ d ≤ 31
0 ≤ d ≤ 31
0 ≤ d ≤ 31
0 ≤ d ≤ 31
0 ≤ d ≤ 31
0 ≤ q ≤ 63
0 ≤ d ≤ 31
0 ≤ d ≤ 31
0 ≤ d ≤ 31
0 ≤ d ≤ 31
0 ≤ q ≤ 63
0 ≤ d ≤ 31
0 ≤ k ≤ 607
0 ≤ r ≤ 31
Flags
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
WN
11
11
11
11
11
11
11
11
11
11
Binary Opcode
1111 01kk kkkk k100
1111 00kk kkkk k100
1111 00kk kkkk k101
1111 01kk kkkk k101
1111 00kk kkkk k110
1111 01kk kkkk k110
1111 00kk kkkk k011
1111 01kk kkkk k011
1111 00kk kkkk k111
1111 01kk kkkk k111
11
11
11
11
11
11
11
11
11
11
11
11
11
11
22
11
0010 11rd dddd rrrr
0000 0001 dddd rrrr
1110 KKKK dddd KKKK
1001 000d dddd 1100
1001 000d dddd 1101
1001 000d dddd 1110
1000 000d dddd 1000
1001 000d dddd 1001
1001 000d dddd 1010
10q0 qq0d dddd 1qqq
1000 000d dddd 0000
1001 000d dddd 0001
1001 000d dddd 0010
10q0 qq0d dddd 0qqq
1001 000d dddd 0000
kkkk kkkk kkkk kkkk
1001 001r rrrr 1100
6. Nov. 2012
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