AMG-XB404 Datasheet, PDF (24/73 Pages) alpha microelectronics gmbh – Fully Integrated Single Motor Controller for Electrical Motors

AMG-XB404
Fully Integrated Single Motor Controller for Electrical Motors
The PWM unit is capable of indicating a faulty current reconstruction by means of the NOI flag in
register 6. The 18 least significant bits form the no-current error vector NOIV. The most significant
seven bits of them indicate an error in calculation of the duty cycle. The three least significant bits
indicate an error in dead-time compensation. The NOI flag is set if any bit of NOIV is set.
The PWM unit requires the offset value of the current channel operation amplifier for current
reconstruction. This floating point value called IOFFS has to be written to address 5 of the register
file and is calculated as: _{IOFFS =2O⋅2}^−22 . With O being the ADC’s integer value with zero
current.
In order to prevent an inverter shoot-through the PWM unit inserts an adjustable delay between the
high-side and low-side active states. The delay value is set via register 3 and is a 9 bit wide
multiple of the MCPU’s clock cycle. The floating point value of this dead-time register is calculated
as: TD=2t _delay⋅ f _FPU⋅2^−22 .
A minimum sample acquisition time is guaranteed by setting the value of register 4, TAQU. The
acquisition time is a 15 bit wide multiple of the MCPU’s clock cycle. The floating point value of the
acquisition time register TAQU is calculated as: TAQU =2t _aqu⋅ f _FPU⋅2^−22 .
5.4.4. Accessing the DMCE via the On-Chip Bus
Bit
7
6
5
4
3
2
1
0
Register Comment
name
Write/Read
D0[7:0]
M0DAT0
Data
register D0
Initial value
0
0
0
0
0
0
0
0
Bits [7..0]
Write/Read
D1[7:0]
M0DAT1
Data
register D1
Initial value
0
0
0
0
0
0
0
0
Bits [15..8]
Write/Read
D2[7:0]
Data
Initial value
0
0
0
0
0
0
0
0
M0DAT2 register D2
Bits
[23..16]
Write/Read
D3[7:0]
Data
Initial value
0
0
0
0
0
0
0
0
M0DAT3 register D3
Bits
[31..24]
Write
ADR[7:0]
M0ADR
Address
Initial value
0
0
0
0
0
0
0
0
register
Write
-
-
-
-
ADR[8]
OP[2:0]
Read
-
-
-
-
-
-
-
START
M0SC
Status and
command
Initial value
-
-
-
-
-
-
-
0
register
Write
-
-
-
-
-
-
-
0
DMCE
Read
-
-
-
-
-
-
-
DMCESEL ^DMCESEL
select
register
Initial value
-
-
-
-
-
-
-
0
Table 10: DMCE access registers
The DMCE has six dedicated 8 bit registers on the 8 bit on-chip bus, see table 10. The DMCE can
only be accessed via the SPI interface if the IC is not locked, see section 5.7.1 page 37. The
DMCESEL flag in the LSB of the DMCE select port determines which DMCE is accessed. If set to
zero DMCE0, i.e. MCPU0, is accessed. Four data ports are used to write and read program or
register data. The 7 bit wide register address is set using the address register. The 9 bit wide
program memory address is set using the address register for the eight least significant bits and bit
three of the command register for the most significant bit. Read and write operations are triggered
by writing the status and command port’s three least significant bits. All available commands are
summarized in table 11.
AMG-XB404
Revision: A
2. Nov. 2012 © All rights reserved
Page 24 of 73