AMG-XB404 Datasheet, PDF (7/73 Pages) alpha microelectronics gmbh – Fully Integrated Single Motor Controller for Electrical Motors

AMG-XB404
Fully Integrated Single Motor Controller for Electrical Motors
5. Block Descriptions
5.1. System SPI Unit and On-Chip Bus
SCLK
SCS
SDI
SDO
EEPROM
Shadow
SRAM
Prog/Debug
Interface
System
SPI
MCU
RISC
core
bus
activity
...
...
8 bit
on-chip bus
Figure 3: SPI bus masters and clients overview
On-chip communication is built around an 8 bit on-chip bus. There are two bus masters: the MCU
core is the primary bus master and the System SPI unit is the secondary bus master. The System
SPI unit is used to program, configure, and debug the AMG-XB404. An activity signal from the
MCU to the System SPI unit indicates activity on the bus, and ensures that the System SPI can
only access the bus if the MCU is not. MCU bus reads and writes can slow down but not inhibit the
execution of System SPI commands. Note that the EEPROM and debug interface can be
accessed via the System SPI only.
There are four basic System SPI commands to write and read data, Table 1 shows an overview.
See table 32 on page 58 for an overview of all 8 bit buses addresses.
Command Description
0
not used
1
write 8 bit data to 5 bit addressed register (see figure 1)
2
read 8 bit data from 5 bit addressed register (see figure 2)
3
write 8 bit data to 5 bit addressed register; wait for LSB=0 at the same address
(see figure Fehler: Referenz nicht gefunden)
4
read 32 bit data from 5 bit addressed register (see figure Fehler: Referenz nicht
gefunden)
Table 1: System SPI commands
The bus employs 6 bit wide addressing. While the MCU may access all 64 addresses, the System
SPI can only access the 32 lower addresses.
System SPI transmissions are framed by the chip select signal SCS, the System SPI unit is active
only when SCS is LOW. The transmission timing is determined by the serial clock signal SCLK.
Data is received via the serial data input signal SDI and sent via the serial data output signal SDO.
Data signals are valid at the rising edge of the serial clock signal. Every transmission starts with
the MSB and ends with an inverted XOR parity bit generated over all previously sent bits. If the
transmission is received correctly, i.e. ends with a valid parity bit, the command will be processed
by the System SPI unit. Handshaking is accomplished by the master waiting for SDO to become
HIGH after issuing a command. In case of an unsuccessful parity check SDO will stay LOW
permanently and a time-out mechanism must take effect on the master’s side. The signal
AMG-XB404
Revision: A
2. Nov. 2012 © All rights reserved
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