AMG-XB404 Datasheet, PDF (23/73 Pages) alpha microelectronics gmbh – Fully Integrated Single Motor Controller for Electrical Motors

AMG-XB404
Fully Integrated Single Motor Controller for Electrical Motors
exceptions. Consequently, any algorithm implemented on the AMG-XB404 must avoid or handle
these limitations in order to prevent malfunction.
5.4.2. Register File
Out of the 128 directly addressed registers, registers 0 through 9 are special purpose registers
reserved for the communication with the PWM unit (see table 9 p. 23).
Registers can be read from and written to by the DMCE and via the 8 bit on-chip bus. Two times 32
indirectly addressed registers can be read from and written to via registers 8 and 9. The address
index is set via register 6. For the details of indirect addressing see table 9.
Address Register Read value
name
Register Write value
name
0
RDY Ready flag, sign bit set at the start of each PWM
NU U-phase PWM value in bits [14:0] of mantissa
cycle
1
IU
U-phase current produced by virtual current sensor,
NV V-phase PWM value in bits [14:0] of mantissa
value in bits [14:0] of the mantissa, offset by 8192
2
IV
V-phase current produced by virtual current sensor,
NW W-phase PWM value in bits [14:0] of mantissa
value in bits [14:0] of the mantissa, offset by 8192
3
VDC DC bus voltage, value in bits [11:0] of the mantissa
TD PWM dead time TD measured in MCPU clock cycles, value in
bits [8:0] of mantissa
4
VDCR 1 divided by DC bus voltage, value contained in bits TAQU Minimum current sample acquisition time TAQU measured in
[22:0] of the mantissa
MCPU clock cycles, value in bits [14:0] of mantissa
5
IOFFS Zero current offset contained in bits [13:0] of
mantissa
IOFFS Zero current offset, value in bits [13:0] of mantissa
6
NOI No current obtained if sign bit of this register is set INDEX Index for indirect addressing, value in bits [22:18] of mantissa
7
MCPUE MCPU enable flag, bit 0 of the mantissa
N
MCPUE MCPU enable flag, if bit 0 of mantissa is set to zero MCPU will be
N
reset
8
IREGA Read from indirect addressed registers A
IREGA Write to indirect addressed registers A
9
IREGB Read from indirect addressed registers B
Table 9: Special purpose registers
IREGB Write to indirect addressed registers B
5.4.3. PWM Unit
The PWM unit is responsible for generating the PWM timings for each of the three phases
according to the duty cycles requested by the MCPU. Voltage vectors are chosen by the PWM unit
to enable a safe reconstruction of the motor's phase currents. Duty cycles are specified by the
values of NU, NV, and NW written to register addresses 0 to 2 (see table 9). For a duty cycle DC
between 0 and 1 the floating point value for NU is calculated as: NU =2 DC⋅2^−22 . The same
equation applies to NV and NW.
Moreover, the PWM unit performs autonomous dead-time compensation by means of the internally
assigned feedback pins RU0/1, RV0/1, RW0/1 ensuring the equality of intended and factual duty
cycle for each phase.
The PWM unit is also in charge of triggering voltage and current sampling at the appropriate time
slots within each PWM cycle and reconstructing the U and V phases’ currents (IU, IV). The 12 bit
wide values of IU and IV are available to the MCPU core through the special purpose registers at
addresses 1 and 2 (see table 9).
The special purpose register at address 3 contains the DC bus voltage floating point value VDC,
which is calculated as: VDC =2VDC _ADC⋅2^−22 . With VDCADC being the DC bus voltage integer
value from the ADC. The inverted DC bus voltage's floating point value VDCR can be accessed at
address 4 and is calculated as:
VDCR=
2
1
VDC
⋅2^−22
ADC
.
AMG-XB404
Revision: A
2. Nov. 2012 © All rights reserved
Page 23 of 73