AMG-XB404 Datasheet, PDF (56/73 Pages) alpha microelectronics gmbh – Fully Integrated Single Motor Controller for Electrical Motors

AMG-XB404
Fully Integrated Single Motor Controller for Electrical Motors
providing a temperature-dependent FLL divider ratio based on a polynomial function of chip
temperature. The initial divider value and the temperature coefficient are measured and stored in
the EEPROM during final test. They can be used by the MCU to perform temperature
compensation in combination with the ADC value of the temperature channel.
An external 8MHz crystal or resonator can be attached to the pins XO and XO_OSEL. The CXO
clock signal generated by the inverter-based oscillator is divided by 256 to obtain a 32µs time
standard. In combination with the default divider ratio a system clock of 64MHz results and no
adjustments to the divider ratio are required.
The AMG-XB404's system clock signal can also be input via the CLKIO pin when configured
appropriately.
In order to prevent external noise from interfering with the clock selection setting, the CLKLOCK
flag can be set via the IO expander. When set, the flag will preserve the selection preset at the time
of setting CLKLOCK, see section 5.2., page 9 for details.
When an internal clock source is selected the CLKIO pin acts as a clock output, allowing for
system clock monitoring. CLKIO output may be disabled by setting CLKOFF within the IO
expander, see section 5.2., page 9 for details.
5.9. Power-On and System Reset
D5V
NPOR
Power-on
Reset
FLL LOCK
short for
external
clock
NRESOUT
short for
internal
clock
NRESIN
Figure 39: AMG-XB404 reset scheme block schematic
LP
System reset
filter
The AMG-XB404 has got a dedicated active-LOW reset signal input pin named NRESIN. The reset
input is low-pass filtered for improved noise rejection. Any reset impulse shorter than 2µs (typical)
will be discarded.
As shown in figure 39 system reset must be handled differently for externally and internally
generated clock signals. For internally generated clocks the active-LOW FLL lock signal at the
output pin NRESOUT must be connected to NRESIN. For externally generated clocks the active-
LOW output pin NPOR of the power-on reset unit must be connected to NRESIN. An external reset
circuit may also feed NRESIN directly but must ensure that the IC operating conditions are
guaranteed as discussed below.
The power-on reset unit monitors the supply voltage D5V and keeps the FLL unit reset while the
supply voltage is too low for supplying the AMG-XB404. When D5V rises above the safe threshold
voltage VPOR the IC's FLL reset signal POR will be released with power-on delay of tPOR. The FLL
will then start to adjust the AMG-XB404's VCO and indicated a frequency lock by setting its lock
signal to LOW, the lock signal can be observed at pin NRESOUT. The start-up to lock time of the
FLL is defined as tLOCK.
AMG-XB404
Revision: A
2. Nov. 2012 © All rights reserved
Page 56 of 73