AMG-XB404 Datasheet, PDF (31/73 Pages) alpha microelectronics gmbh – Fully Integrated Single Motor Controller for Electrical Motors

AMG-XB404
Fully Integrated Single Motor Controller for Electrical Motors
ADDR Type
27
Name or value
DCNT
Number of valid bits
10
28
ENDL
13
29
ENDH
13
32..63 SRAM SRAM0 ... SRAM31
16
Table 13: Data memory overview (constants and hardware ports are used as registers)
The PFC controller uses center-aligned PWM signals as shown in figure 18. The start and end of a
PWM cycle are determined by the PWM reference counter's maximum value which equals the
value of the ENDH register divided by two.
The PWM period has thus a multiple of ENDH / f _FPU . ENDH is double buffered, i.e. its value
can be set at any time by writing the value to the buffer ENDH but will only be applied to the
internally used register ENDHi in the next PWM cycle. Consequently, randomized duty cycles can
be set asynchronously. The duty cycle of the PWM is determined by the ratio of ENDHi and ENDLi,
i.e. DC =ENDLi / ENDHi . ENDL is double buffered as well and will be updated to its internally
used register ENDLi at the same time as ENDH to ENDHi (see figure 18).
Due to the low-pass filtered characteristic of the current signal its sampling must be delayed
relative to the PWM signal. Setting the value of the DELAY register will postpone current sampling
by an adjustable number of PFC clock cycles. Each sampling of the rectified AC current is followed
by a sampling of the rectified AC voltage. The DC bus voltage value is updated whenever a new
sample delivered to the DMCE core. The PFC has no means of triggering DC voltage value
sampling.
Normally, calculation and sample acquisition are synchronized by the means of the PFC
controller's SYNC operation which halts execution until the LSB of the PFC_IAC register becomes
1, indicating the completion of rectified AC current sampling. The PFC_IAC register can also be
read directly.
AMG-XB404
Revision: A
2. Nov. 2012 © All rights reserved
Page 31 of 73