AMG-XB404 Datasheet, PDF (49/73 Pages) alpha microelectronics gmbh – Fully Integrated Single Motor Controller for Electrical Motors

AMG-XB404
Fully Integrated Single Motor Controller for Electrical Motors
Bit
7
6
5
Write
Read
Initial value
0
0
0
Write
-
MODE[1:0]
Read
-
MODE[1:0]
Initial value
0
0
0
Table 24: SPI registers
4
3
DATA[7:0]
DATA[7:0]
0
0
SPIEN
MSBLSB
SPIEN
MSBLSB
0
0
2
0
CSEN
CSEN
0
1
0
-
WCOL
-
0
Register Comment
name
SPIDAT
Data
register
0
-
Control
TRF
SPICTRL
register
-
SPI master
SPI slave
SCLKO
SCSO
TXB
SDO
012 345 67
RXB
SDI
765 432 10
SCLKI
SCSI
SDI
RXB
01 234 567
SDO
TXB
76 543 210
Figure 32: SPI communication principle
To enable the SPI the flag SPIEN has to be set to 1. With the MSBLSB flag set to 1 the MSB will
be transferred first, otherwise the LSB is transferred first. The flag CSEN controls the usage of the
chip select line, if set to 1 chip select is used, otherwise chip select will be ignored.
WCOL and TRF are read-only flags for write collision WCOL and readiness for next transmission
TRF. In master mode a collision occurs if new data is written to SPIDAT while the previous
transmission has not been finished. The SPI’s mode controls master/slave operation and the serial
clock speed in master mode. It is selected by setting MODE[1:0] as shown in table 25.
Mode
CTRL[6] CTRL[5] Clock speed
Master
0
0
2 MHz
Master
0
1
500 kHz
Master
1
0
125 kHz
Slave
1
1
-
Table 25: SPI mode selection
The SPI has got a single interrupt flag which can be enabled through the interrupt control register
(see section 5.2.22 p. 15). The interrupt is raised after each completed transmission. The interrupt
flag is cleared by reading from or writing to SPIDAT.
5.7.5. Two Wire Interface (TWI)
The GPIO’s PORTB[2] and PORTB[3] become the two wire interface's serial clock SCL and serial
data SDA pins when the TWI is enabled by setting TWENA in CONFIG_REG to 1 (see table 26). A
pull-up resistor is required at each pin. The two wire interface can be configured to operate in
master or slave mode by setting MODE in CONFIG_REG, master mode is enabled by setting the
flag to 1. The TWI master can initiate writes to and reads from a TWI slave.
AMG-XB404
Revision: A
2. Nov. 2012 © All rights reserved
Page 49 of 73