AMG-XB404 Datasheet, PDF (52/73 Pages) alpha microelectronics gmbh – Fully Integrated Single Motor Controller for Electrical Motors

AMG-XB404
Fully Integrated Single Motor Controller for Electrical Motors
5.7.6. General Purpose Timers
The AMG-XB404 has got two 8 bit timers and one 16 bit timer. All timers are controlled by the MCU
via the on-chip bus. Each timer has got one dedicated interrupt generated by match and input
capture timer events. Timer interrupts can be enabled independently. Interrupt flags are cleared
automatically upon timer interrupt execution or IC reset. Table 29 lists all timer-related registers.
Each timer can be configured to use an individual system clock pre-scaler ratio.
Timers have got an 8 or 16 bit wide counter register CNT, which can be read from and written to,
and an output compare register OCR, containing the compare value for the timer match function,
which also can be read from and written to. Each timer’s control register contains the individual
timer’s pre-scaler setting in its least significant 3 bits (see table 28). The timer will be disabled if the
pre-scaler is set to 0.
PRESCALER[2:0] Timer reference clock
0
timer off
1
MCU clock frequency
2
MCU clock frequency divided by 2
3
MCU clock frequency divided by 4
4
MCU clock frequency divided by 16
5
MCU clock frequency divided by 64
6
MCU clock frequency divided by 256
7
MCU clock frequency divided by 512
Table 28: Clock modes for 8 bit and 16 bit timers
If the timer is enabled the timer’s counter register will be incremented according to the pre-scaler
setting. If the counter overflows CNT changes from 65535 to 0 (16 bit timer) or 255 to 0 (8 bit
timers).
Each timer has got two principle modes, match mode and input capture mode. Match mode is
always active. In addition input capture mode can be enabled if input capture enable ICEN is set
to 1.
In match mode (see figure 36) the interrupt flag is set if CNT equals OCR, and interrupt enable
INTEN in TCR is set to 1. If reset on match ROM in TCR is set to 1 CNT will be reset to 0. An
interrupt on match is only generated if input capture enable ICEN is set to 0.
OCR
CNT
OC
INT
ROM
Figure 36: Timer match mode (assuming
immediate interrupt handling)
By setting OCEN and the according GPIO PORTB output enable to 1 the output compare output
OC is enabled (see table 21 p. 47). OC is set to 0 on reset and will be toggled on match if reset on
match is enabled. By writing to TCR[4] OC can be pre-set. If reset on match is disabled OC is set
to 0 on match and set to 1 on counter overflow.
AMG-XB404
Revision: A
2. Nov. 2012 © All rights reserved
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