AMG-XB404 Datasheet, PDF (50/73 Pages) alpha microelectronics gmbh – Fully Integrated Single Motor Controller for Electrical Motors

AMG-XB404
Fully Integrated Single Motor Controller for Electrical Motors
The TWI address register and TWI address mask register share the same MCU bus address. The
MSB determines which register is set if written to. Reading the register returns the TWI address
register, the address mask register cannot be read. If the address set by the master (ADDR)
masked by TWIAM and the address set in the slave TWIA masked by TWIAM match, the address
is considered valid. This can be expressed as ADDR ∧TWIAM =TWIA∧TWIAM , ∧ denotes
a bit-wise AND. With a TWIAM set to binary 1111100 addresses 124, 125, 126 and 127 can be
addressed.
Bit
7
6
Write
Initial value
Read
Initial value
Write
TWENA
0
FLAG
0
1
-
-
RSTART
0
Write
0
Read
0
Initial value
0
0
Write
Read
Initial value
0
0
Table 26: TWI registers
5
MODE
1
RSTOP
0
0
0
4
3
2
1
0
RW
STARTREG STOPREG
PRESCALER[1:0]
0
0
0
0
0
RW
STARTREG STOPREG DATAWF DATARF
0
0
0
0
0
ADDRM[6:0]
ADDR[6:0]
ADDR[6:0]
0
0
0
0
0
DATA[7:0]
DATA[7:0]
0
0
0
0
0
Register
name
TWISC
TWIADR
Comment
Configuration
register;
write-only
Status
register;
read-only
Address
mask register
Address
register
TWIDAT
Data register
SDA
SCL
START
Change Sample
SDA
SDA
STOP
Figure 33: Start stop conditions
State changes of the serial data line SDA when the serial clock SCL is HIGH indicate either the
start condition (falling edge of SDA) or the stop condition (rising edge of CLK). Consequently, SDA
may only change its state when SCL is LOW during data transfers, master and slave must sample
SDA when SCL is HIGH (see figure 33).
Every start condition is followed by an address cycle as shown in figure 34. The 7 bit wide address
is transmitted with its MSB first and is followed by the read/write flag. Data is transmitted from
master to slave if this flag is set to 0 and from slave to master if set to 1. The slave acknowledges
an address cycle by pulling SDA to LOW during the clock cycle following the read/write flag. In
slave mode the TWI will only acknowledge the address cycle if the sent address and the TWI’s
address mask are valid. An address cycle can be followed by a data cycle or a stop condition.
AMG-XB404
Revision: A
2. Nov. 2012 © All rights reserved
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