AMG-XB404 Datasheet, PDF (39/73 Pages) alpha microelectronics gmbh – Fully Integrated Single Motor Controller for Electrical Motors

AMG-XB404
Fully Integrated Single Motor Controller for Electrical Motors
If no EEPROM is found reset will not be released, and a “no detect” status will be indicated via the
unit's status and command register.
5.7.1.2. Shadow SRAM Reads and Writes
For quick MCU program development the IC's Shadow SRAM can be read and written. Before
reading and writing the MCU needs to be reset using command 2 detailed in Table 17.
In order to execute writes to Shadow SRAM memory the 16 bits of data of the program word are
written to the two 8 bit data registers, SRD0 and SRD1. Next, the 14 bit wide address is written to
SRA0 and SRA1[5:0]. The actual write is initiated by writing command 0 to the status and
command register SRSC.
In order to execute a read from Shadow SRAM memory, the 14 bit address is written to SRA0 and
SRA1[5:0]. By writing command 1 to SRSC the SRAM read is executed and the 16 bits of data can
be read from SRD0 and SRD1 via the 8 bit on-chip bus after SRSC[0] has been read as 0.
5.7.1.3. EEPROM Rads and Writes
To permanently store program and configuration data the EEPROM is used. Each byte inside the
EEPROM corresponds to one half of a Shadow SRAM program word. EEPROM address 0
contains the low-byte of Shadow SRAM address 0, EEPROM address 1 contains the high-byte of
Shadow SRAM address 0, EEPROM address 2 contains the low-byte of Shadow SRAM address 1,
etc.
Serial two-wire communication is performed via port 40 of the IO expander (see table 2b, p. 14),
and is activated by enabling engineering mode via port 1 of the IO expander. Figure 20 shows the
start and stop conditions
SDA
SCL
START
Change Sample
SDA
SDA
STOP
Figure 20: Two-wire communication start stop
conditions
State changes of the serial data line SDA when the serial clock SCL is HIGH indicate either the
start condition (falling edge of SDA) or the stop condition (rising edge of CLK). Consequently, SDA
may only change its state when SCL is LOW during data transfers, master (IO expander) and slave
(EEPROM) must sample SDA when SCL is HIGH (see figure 20).
Every start condition is followed by an address cycle as shown in figure 21. The 7 bit wide address
is transmitted with its MSB first and is followed by the read/write flag. Data is transmitted from
IO expander to EEPROM if this flag is set to 0 and from slave to master if set to 1. The EEPROM
acknowledges an address cycle by pulling SDA to LOW during the clock cycle following the
read/write flag. In slave mode the two wire communication interface will only acknowledge the
address cycle if the sent address and the address mask are valid. An address cycle can be
followed by a data cycle or a stop condition.
AMG-XB404
Revision: A
2. Nov. 2012 © All rights reserved
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