AK4497 Datasheet, PDF (92/98 Pages) Asahi Kasei Microsystems – Quality Oriented 32-Bit 2ch DAC

[AK4497]
1. Grounding and Power Supply Decoupling
To minimize coupling by digital noise, decoupling capacitors should be connected to AVDD, TVDD, DVDD,
VDDL and VDDR. AVDD and VDDL/R are supplied from analog supply in system, and TVDD and DVDD
are supplied from digital supply in system. Power lines of VDDL/R should be distributed separately from
the point with low impedance of regulator etc. When not using LDO (LDOE pin = “L”), AVDD and TVDD
should be powered up before or at the same time of DVDD. When using LDO (LDOE pin = “H”), power up
sequence between AVDD/TVDD and VDDL/R are not critical. AVSS, DVSS, VSSL and VSSR must be
connected to the same analog ground plane. Decoupling capacitors for high frequency should be
placed as near as possible to the supply pin.
2. Voltage Reference
The differential voltage between VREFHL/R and VREFLL/R sets the full scale of the analog output range.
The VREFHL/R pin is normally connected to VDD, and the VREFLL/R pin is normally connected to VSS.
VREFHL/R and VREFLL/R should be connected with a 0.1µF ceramic capacitor and a 2200uF electrolytic
capacitor as near as possible to the pin to eliminate the effects of high frequency noise.
The VREFH and VREFL pins should be treated to not have noises from other supply pins. If the analog
characteristics cannot satisfy the specification by this noise, connect the VREFH to analog 5.0V via a 10 Ω
resistor and connect the VREFL pin to the analog ground via a 10 Ω resistor. (A low-pass filter of fc=500Hz
will be composed by a 2200uF capacitor and a 10Ω resistor. This low-pass filter removes signal frequency
noise from other power supply pins.)
VCML/R is a common voltage of this chip. No load current may be drawn from the VCML/R pin. All signals,
especially clocks, should be kept away from the VREFHL/R and VREFLL/R pins in order to avoid
unwanted noise coupling into the AK4497.
3. Analog Outputs
The analog outputs are full differential outputs. The differential outputs are summed externally, V_AOUT =
(AOUT+)  (AOUT) between AOUT+ and AOUT. If the summing gain is 1, the output range of the setting
the GAIN pin = “L” or GC[2] bit = “0” is 2.8Vpp (typ, VREFHL/R  VREFLL/R = 5V) centered around VCML
and VCMR voltages. In this case, the output range after summing will be 5.6V (typ.). The output range of
the setting the GAIN pin = “H” or GC[2] bit = “1” is 3.75Vpp (typ.) centered around VCML and VCMR
voltages. In this case, the output range after summing will be 7.5Vpp (typ.). The bias voltage of the external
summing circuit is supplied externally.
The input data format is 2's complement. The output voltage (V_AOUT) is a positive full scale for 7FFFFFFFH
(@32bit) and a negative full scale for 80000000H (@32bit). The ideal V_AOUT is 0V for 00000000H (@32bit).
The internal switched-capacitor filters attenuate the noise generated by the delta-sigma modulator beyond
the audio passband. Figure 70 and Figure 71 show examples of external LPF circuit summing the
differential outputs by a single op-amp. Figure 72 shows an example of differential output circuit and
external LPF circuit with two op-amps. Figure 73 shows an example of external LPF circuit with two
op-amps when MONO bit = “1”. A resistor that has 0.1% or less absolute error must be used for external
LPFs.
AK4497
AOUT-
AOUT+
300
43n
100
130n 100
300
30 6.8n
+Vop
10
20n
2
7
6
3
4
-Vop
OPA1611
Analog
Out
Figure 70. External LPF Circuit Example 1 (fc = 98kHz(typ), Q=0.667(typ))
Rev. 0.1
- 92 -
2015/11