AK4497 Datasheet, PDF (43/98 Pages) Asahi Kasei Microsystems – Quality Oriented 32-Bit 2ch DAC

[AK4497]
[1] DSD Mode
The AK4497 has a DSD playback function. The external clocks that are required in DSD mode are MCLK
and DCLK. MCLK should be synchronized with DCLK but the phase is not critical. The frequency of
MCLK is set by DCKS bit (Table 19).
The AK4497 is automatically placed in power-down state when MCLK is stopped during a normal
operation (PDN pin =“H”), and the analog output becomes Hi-z state. When the reset is released (PDN
pin = “L” → “H”), the AK4497 is in power-down state until MCLK and DCLK are input.
Table 19. System Clock (DSD Mode, fs=32kHz, 44.1kHz, 48kHz)
DCKS bit MCLK Frequency DCLK Frequency
0
512fs
64fs/128fs/256fs (default)
1
768fs
64fs/128fs/256fs
The AK4497 supports DSD data stream of 2.8224MHz (64fs), 5.6448MHz (128fs) and 11.2896MHz
(256fs). The data sampling speed is selected by DSDSEL[1:0] bits (Table 20).
DSDSEL1
0
0
1
1
DSDSEL0
0
1
0
1
Table 20. DSD data stream select
DSD data stream
fs=32kHz
fs=44.1kHz
2.048MHz
2.8224MHz
4.096MHz
5.6448MHz
8.192MHz
11.2896MHz
16.284MHz
22.5792MHz
fs=48kHz
3.072MHz
6.144MHz
12.288MHz
24.576MHz
(default)
The AK4497 has a Volume bypass function for play backing DSD signal. Two modes are selectable by
DSDD bit (Table 21). When setting DSDD bit = “1”, the output volume control and zero detect functions
are not available.
Table 21. DSD Play Back Path Select
DSDD
Mode
0
Normal Path (default)
1
Volume Bypass
Rev. 0.1
- 43 -
2015/11