AK4497 Datasheet, PDF (55/98 Pages) Asahi Kasei Microsystems – Quality Oriented 32-Bit 2ch DAC

[AK4497]
(2) TDM256 Mode
Figure 42 shows daisy chain connection in TDM256 mode (TDM[1:0] bits = “10”). 8ch data is input to the
SDATA pin of the second AK4497 and the TDMO pin of the second AK4497 is connected to the SDATA
pin of the first AK4497.
Figure 44 shows data input/output example of daisy chain in TDM256 mode. The second AK4497
receives L4 and R4 data as DAC inputs and outputs the data from the TDMO pin by shifting 2ch. The first
AK4497 receives L3 and R3 data as DAC input. Settings of DIF[2:0] bits of the first and second AK4497’s
must be the same.
LRCK
SDATA
TDMO
256 BICK
L1
R1
L2
R2
L3
R3
L4
R4
Second AK4497
L4
R4
L1
R1
L2
R2
L3
R3
First AK4497
Figure 44. Daisy Chain (TDM256 Mode)
[2] DSD Mode
In DSD mode, L channel data and R channel data must be input to the DSDL pin and the DSDR pin,
respectively by synchronizing to DCLK. Input pins can be selected by DSDPATH bit. When DSDPATH bit
= “0”, the TDM0 pin, the DEM pin and the GAIN pin become DCLK, DSDL and DSDR input pins,
respectively. When DSDPATH bit = “1”, the BICK pin, the SDATA pin and the LRCK pin become DCLK,
DSDL and DSDR input pins, respectively.
In case of DSD mode, the settings of DIF2-0 pins and DIF[2:0] bits are ignored. The frequency of DCLK is
selected between 64fs, 128fs and 256fs by DSDSEL[1:0] bits. Phase modulation function is not available
in 512fs mode (DSDSEL[1:0] bits = “11”).
DCLK (64fs,128fs,256fs,512fs)
DCKB bit=”1”
DCLK (64fs,128fs,256fs,512fs)
DCKB bit=”0”
DSDL,DSDR
D0
D1
Normal
D2
D3
DSDL,DSDR
Phase Modulation ^D0
D1
D1
D2
D2
D3
Figure 45. DSD Mode Timing
Rev. 0.1
- 55 -
2015/11