AK4497 Datasheet, PDF (71/98 Pages) Asahi Kasei Microsystems – Quality Oriented 32-Bit 2ch DAC

[AK4497]
(2) Power ON/OFF by PW bit
All circuits including control register and IREF (except LDO when the LDOE pin = “H”) stop operation by
setting PW bit to “0”. In this case, control register access is available. The analog output goes to floating
state (Hi-Z). Figure 55 shows power ON/OFF sequence by PW bit.
PW bit
RSTN bit
Internal
State
DAC In
(Digital)
DAC Out
(Analog)
DZFL/DZFR
Normal Operation
Power-off
“0” data
(1)
GD
(3) (2) Hi-z
(4)
Normal Operation
GD (1)
(3)
External
MUTE
(5)
Mute ON
Notes:
(1) The analog output corresponding to the digital input has group delay (GD).
(2) The analog output is floating (Hi-Z) state when PW bit = “0”.
(3) Click noise occurs at the edge of PW bit. This noise is output even if “0” data is input.
(4) The zero detect function is enable when the AK4497 is power off (PW bit= “0”). This figure shows
the seuqnece when DZFE bit= “1”, DZFB bit = “0” and DZFM bit= “0”.
(5) Mute the analog output externally if click noise (3) or Hi-z output (2) adversely affect system
performance.
Figure 55. Power ON/OFF Timing Example
Rev. 0.1
- 71 -
2015/11