AK4497 Datasheet, PDF (63/98 Pages) Asahi Kasei Microsystems – Quality Oriented 32-Bit 2ch DAC

[AK4497]
■ DSD Signal Full Scale (FS) Detection
The AK4497 has independent full scale detection function for each channel for DSD mode.
The AK4497 detects full scale signal when the DSDL/R input data is continuously “0” (-FS) or “1” (+FS) for
2048 cycles and the detection flag for corresponding channel (DML or DMR bit) becomes “1”. DML and
DMR bits can be read out at the register address 06H.
When the AK4497 detects full scale signal while DDM bit = “1”, the analog output is muted in ATT
transition period set by ATS[2:0] bits. This transition is executed by soft transition when DSDD bit = “0”.
The analog output is muted immediately when DSDD bit = “1”. These settings (ATS[2:0] bits and DSDD
bits) are also valid when the AK4497 returns to normal status from full scale detection status.
The recovery timing from full scale detection status is controlled by DMC bit when DDM bit = “1”. When
DMC bit = “0”, the AK4497 is automatically recovered and transitions to normal operation by a normal
signal input. When DMC bit = “1”, the AK4497 transitions to normal operation by setting DMRE bit = “1”
while normal signal is input. DMRE bit automatically returns to “0” when the transition is finished. When
DDM bit = “1”, full scale signal can be detected but the AK4497 does not change to mute status. RSTN bit
must be set to “0” when changing DDM bit setting.
Table 39. DSD Mode and Device Status after Full-Scale Detection (DDM bit= “1”)
DSDD
Mode
Full Scale Detection Status Analog Output
0
Normal Path
DSD Mute
VCML/R
(default)
1
Volume Bypass
Digital Reset
VCM/L/R
DSD Data
DSD Data
DSD Error
(DML or DMRbit)
AOUT
(DSDD bit= “0”)
DSD Data (FS or -FS )
2048fs
ATT Transition Period
DSD Data
ATT Transition Period
AOUT
(DSDD bit= “1”)
Figure 47. Analog Output Waveform in DSD FS Detection (DMC bit= “0”)
DSD Data
DSD Data
DSD Error
(DML or DMRbit)
DSD Data (FS or -FS )
2048fs
DMRE bit
AOUT
(DSDD bit= “0”)
ATT Transition Period
DSD Data
ATT Transition Period
AOUT
(DSDD bit= “1”)
Figure 48. Analog Output Waveform in DSD FS Detection (DMC bit= “1”)
Rev. 0.1
- 63 -
2015/11