AK4497 Datasheet, PDF (83/98 Pages) Asahi Kasei Microsystems – Quality Oriented 32-Bit 2ch DAC

[AK4497]
Addr Register Name
02H Control 3
R/W
Default
D7
D6
D5
D4
D3
D2
D1
D0
DP
0
DCKS DCKB MONO DZFB SELLR SLOW
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
SLOW: Slow Roll-off Filter Enable. (Table 27)
0: Slow roll-off filter disable (default)
1: Slow roll-off filter
SELLR: The data selection of L channel and R channel, when MONO mode
0: All channel output L channel data, when MONO mode. (default)
L channel output L channel data, Rchannel data output Rchannel data(default)
1: All channel output R channel data, when MONO mode.
L channel output R channel data, Rchannel data output Lchannel data
DZFB: Inverting Enable of DZF. (Table 34)
0: DZF pin goes “H” at Zero Detection (default)
1: DZF pin goes “L” at Zero Detection
MONO: MONO mode Stereo mode select
0: Stereo mode (default)
1: MONO mode
DCKB: Polarity of DCLK (DSD Only)
0: DSD data is output from DCLK falling edge. (default)
1: DSD data is output from DCLK rising edge.
DCKS: Master Clock Frequency Select at DSD mode (DSD only)
0: 512fs (default)
1: 768fs
DP: DSD/PCM Mode Select
0: PCM Mode (default)
1: DSD Mode
When DP bit is changed, the AK4497 should be reset by RSTN bit.
Rev. 0.1
- 83 -
2015/11