AK4497 Datasheet, PDF (23/98 Pages) Asahi Kasei Microsystems – Quality Oriented 32-Bit 2ch DAC

[AK4497]
■ Switching Characteristics
(Ta=-40~85C; VDDL/R=4.755.25V, TVDD=AVDD=1.73.6V, DVDD=1.7~1.98V, C_L=20pF)
Parameter
Symbol Min.
Typ.
Max.
Unit
Master Clock Timing
Frequency
Duty Cycle
Minimum Pulse Width
fCLK
dCLK
tCLKH
tCLKL
2.048
40
9.155
9.155
49.152
60
MHz
%
nsec
nsec
LRCK Clock Timing (Note 29)
Normal Mode (TDM[1:0] bits = “00”)
Normal Speed Mode
fsn
8
54
kHz
Double Speed Mode
fsd
54
108
kHz
Quad Speed Mode
fsq
108
216
kHz
Oct speed mode
fso
384
kHz
Hex speed mode
fsh
768
kHz
Duty Cycle
Duty
45
55
%
TDM128 mode (TDM[1:0] bits = “01”)
Normal Speed Mode
fsn
8
54
kHz
Double Speed Mode
fsd
54
108
kHz
Quad Speed Mode
fsq
108
216
kHz
High time
tLRH 1/128fs
nsec
Low time
tLRL 1/128fs
nsec
TDM256 mode (TDM[1:0] bits = “10”)
Normal Speed Mode High time
fsn
8
54
kHz
Double Speed Mode
fsd
54
108
kHz
High time
tLRH 1/256fs
nsec
Low time
tLRL 1/256fs
nsec
TDM512 mode (TDM[1:0] bits = “11”)
Normal Speed Mode
fsn
8
54
kHz
High time
tLRH 1/512fs
nsec
Low time
tLRL 1/512fs
nsec
Note 29. The MCLK frequency must be changed while the AK4497 is in reset state by setting the PDN pin
= “L” or RSTN bit = “0”.
Rev. 0.1
- 23 -
2015/11