AK4497 Datasheet, PDF (70/98 Pages) Asahi Kasei Microsystems – Quality Oriented 32-Bit 2ch DAC

[AK4497]
■ Power-OFF/Reset Function
Power-off and Reset function of the AK4497 are controlled by PW bit, RSTN bit and MCLK (Table 42).
Mode
Power Down
MCLK Stop
Power OFF
Reset
Normal Operation
PDN
Pin
L
H
H
H
H
Table 42. Power Off, Reset Function
MCLK PW RSTN DIGITAL ANALOG
Supply bit bit Block Block
－
－－
OFF
OFF
No － －
OFF
OFF
Yes 0
－
OFF
OFF
Yes 1
0
OFF
ON
Yes 1
1
ON
ON
LDO
Register
OFF
ON
ON
ON
ON
Analog Output
Hi-Z
Hi-Z
Hi-Z
VCML/R
Signal Output
(1) Power ON/OFF by MCLK Clock
The AK4497 detects a clock stop and all circuits including MCLK stop detection circuit, control register
and IREF (except LDO when the LDOE pin = “H”) stop operation if MCLK is not input for 1us (min.) during
operation (PDN pin = “H”). In this case, the analog output goes floating state (Hi-Z). The AK4497 returns
to normal operation if PW bit and RSTN bit are “1” after starting to supply MCLK again. The zero detect
function is disabled when MCLK is stopped.
PDN pin
Internal
State
Clock In
MCLK,
D/A In
(Digital)
D/A Out
(Analog)
Normal Operation
(4)
Power-off
MCLK Stop
(3)
(1)
(1)
(2) Hi-z
Normal Operation
Notes:
(1) The AK4497 detects MCLK stop and becomes power off state when MCLK edge is not detected for
1us (min.) during operation.
(2) The analog output goes to floating state (Hi-Z).
(3) Click noise can be reduced by inputting “0” data when stopping and resuming MCLK supply.
(4) Resume MCLK input to release the power-off state by MCLK. In this case, power-up sequence by
the PDN pin or power-on sequence by PW bit are not necessary.
Figure 54. Power ON/OFF by MCLK Clock
Rev. 0.1
- 70 -
2015/11