AK4497 Datasheet, PDF (25/98 Pages) Asahi Kasei Microsystems – Quality Oriented 32-Bit 2ch DAC

[AK4497]
Parameter
Symbol Min.
Typ.
PCM Audio Interface Timing
Normal Mode (TDM[1:0] bits = “00”)
BICK Period
Normal Speed Mode
Double Speed Mode
Quad Speed Mode
Oct speed mode
Hex speed mode
BICK Pulse Width Low
BICK Pulse Width High
tBCK
tBCK
tBCK
tBCK
tBCK
tBCKL
tBCKH
1/256fsn
1/128fsd
1/64fsq
1/64fso
1/64fsh
9
9
BICK “” to LRCK Edge
(Note 31) tBLR
5
LRCK Edge to BICK “”
(Note 31) tLRB
5
SDATA Hold Time
tSDH
5
SDATA Setup Time
tSDS
5
TDM128 mode (TDM[1:0] bits = “01”)
BICK Period
Normal Speed Mode
Double Speed Mode
Quad Speed Mode
BICK Pulse Width Low
BICK Pulse Width High
tBCK
tBCK
tBCK
tBCKL
tBCKH
1/128fsn
1/128fsd
1/128fsq
14
14
BICK “” to LRCK Edge
(Note 31) tBLR
14
LRCK Edge to BICK “”
(Note 31) tLRB
14
SDATA Hold Time
tSDH
5
SDATA Setup Time
tSDS
5
TDM256 mode (TDM[1:0] bits = “10”)
BICK Period
Normal Speed Mode
Double Speed Mode
(Note 32)
BICK Pulse Width Low
BICK Pulse Width High
BICK “” to LRCK Edge
(Note 31)
LRCK Edge to BICK “”
(Note 31)
TDMO Setup time BICK “”
TDMO Hold time BICK “” (Note 34)
SDATA Hold Time
SDATA Setup Time
tBCK
tBCK
tBCKL
tBCKH
tBLR
tLRB
tBSS
tBSH
tSDH
tSDS
1/256fsn
1/256fsd
14
14
14
14
5
5
5
5
TDM512 mode (TDM[1:0] bits = “11”)
BICK Period
Normal Speed Mode
BICK Pulse Width Low
BICK Pulse Width High
BICK “” to LRCK Edge
(Note 33)
(Note 31)
tBCK
tBCKL
tBCKH
tBLR
1/512fsn
14
14
14
LRCK Edge to BICK “”
(Note 31) tLRB
14
TDMO Setup time BICK “”
tBSS
5
TDMO Hold time BICK “” (Note 34) ^tBSH
5
SDATA Hold Time
tSDH
5
SDATA Setup Time
tSDS
5
Note 31. BICK rising edge must not occur at the same time as LRCK edge.
Note 32. Daisy Chain Mode, fsd (max) = 96 kHz if “TVDD < 3.0V”.
Note 33. Daisy Chain Mode, fsn (max) = 48 kHz if “TVDD < 3.0V”.
Note 34. LDOE pin = “L”, tBSH (min) = 4 nsec if “TVDD > 2.6V”.
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Rev. 0.1
- 25 -
2015/11