AK4497 Datasheet, PDF (10/98 Pages) Asahi Kasei Microsystems – Quality Oriented 32-Bit 2ch DAC

[AK4497]
■ Analog Characteristics
8. Electrical Characteristics
(Ta=25C; LDOE=L, AVDD=TVDD=DVDD=3.3V; AVSS=DVSS=VSSL/R=0V;
VREFHL/R=VDDL/R=5.0V, VREFLL/R= 0V; Input data = 24bit; R_L  1k; BICK=64fs; Signal Frequency =
1kHz; Sampling Frequency = 44.1kHz; Measurement bandwidth = 20Hz ~ 20kHz; External Circuit: Figure
72; unless otherwise specified.)
Parameter
Min.
Typ.
Max.
Unit
Resolution
-
-
32
Bits
Dynamic Characteristics
(Note 8)
THD+N
fs=44.1kHz 0dBFS
BW=20kHz 60dBFS
-
-115
TBD
dB
-
-64
TBD
dB
fs=96kHz 0dBFS
-
-113
TBD
dB
BW=40kHz 60dBFS
-
-61
TBD
dB
fs=192kHz 0dBFS
-110
TBD
dB
BW=40kHz 60dBFS
-61
TBD
dB
BW=80kHz 60dBFS
-58
TBD
dB
Dynamic Range (60dBFS with A-weighted)(Note 9, Note 11) 122
127
-
dB
S/N (A-weighted)
(Note 10, Note 11) 122
127
-
dB
S/N (Mono mode, A-weighted)
(Note 11) 125
130
-
dB
Interchannel Isolation (1kHz)
110
120
-
dB
DC Accuracy
Interchannel Gain Mismatch
-
0.15
0.3
dB
Gain Drift
(Note 12)
-
20
ppm/
C
Output Voltage
(Note 13) 2.65
2.8
2.95 Vpp
Output Voltage (GC[2:0]=000)
3.55 3.75
3.95
Load Resistance (HLOAD=L)
(Note 14)
-
-
-
k
Load Resistance (HLOAD=H)
120

Load Capacitance
(Note 14)
-
-
25
pF
Note 8. Measured by Audio Precision System Two. Averaging mode.
Note 9. Figure 72 External LPF Circuit Example. 101dB at 16bit data and 118dB at 20bit data.
Note 10. Figure 72 External LPF Circuit Example. S/N does not depend on the input data size.
Note 11. SC[1:0] bits = “00” or “01”
Note 12. The voltage on (VREFH  VREFL) is held +5V externally.
Note 13. Full scale voltage(0dB). Output voltage scales with the voltage of (VREFHL/R  VREFLL/R).
AOUT (typ.@0dB) = (AOUT+)  (AOUT) = 2.8Vpp  (VREFHL/R  VREFLL/R)/5.
Note 14. Regarding Load Resistance, AC load is 1k (min) with a DC cut capacitor. DC load is 1.5k ohm
(min) without a DC cut capacitor. The load resistance value is with respect to ground. Analog
characteristics are sensitive to capacitive load that is connected to the output pin. Therefore the
capacitive load must be minimized.
Rev. 0.1
- 10 -
2015/11