AK4497 Datasheet, PDF (91/98 Pages) Asahi Kasei Microsystems – Quality Oriented 32-Bit 2ch DAC

[AK4497]
DSP
Micro-
Controller
10. Recommended External Circuits
Digital 3.3V Digital 1.8V
AVDD 3.3V
10u +
10u
+ 1u
+
33k
470u
+
10u
0.1u
0.1u
0.1u
+
Analog 5.0V
Lch Lch _{Lch Out}
LPF Mute
1 _LDOE
2 PDN
3 _BICK/BCK
4 _SDATA/DINL
5 _LRCK/DINR
6 _SSLOW/WCK
7 TDMO
8 ^SMUTE/CSN
9 ^SD/CCLK/SCL
10 ^{SLOW/CDTI/SDA}
11 DIF0/DZFL
12 DIF1/DZFR
13 DIF2/CAD0
14 PSN
15 HLOAD/I2C
16 ^DEM0/DSDL
AOUTLP ⁴⁸
0.1u 10u _AOUTLP 47
+
VDDL 46
VDDL 45
VDDL 44 _0.1u
+
VSSL 43
10u
VSSL 42
VSSL 41
VSSR 40
N _{VSSR 39}
N
VSSR 38
0.1u
VDDR 37
+
10u
VDDR 36
VDDR 35
AOUTRP 34
AOUTRP 33
+
Electrolytic Capacitor
Ceramic Capacitor
Resistor
0.1u
+
+ _470u
10u
Rch Rch _{Rch Out}
LPF Mute
Notes:
- Chip Address = “00”. BICK = 64fs, LRCK = fs
- Power lines of AVDD, TVDD, VDDL and VDDR should be distributed separately from the point
with low impedance of regulator etc.
- AVSS, DVSS, VSSL and VSSR must be connected to the same analog ground plane. (Analog
ground should has low impedance as a solid pattern. THD+N characteristics will degrade if there
are impedances between each VSS.)
- THD+N characteristics will degrade by high frequency noise of MCLK. Connect a 51 Ω damping
resistor to the MCLK pin.
- When AOUT drives a capacitive load, some resistance should be connected in series between
AOUT and the capacitive load.
- All input pins except pull-down/pull-up pins should not be allowed to float.
Figure 69. Typical Connection Diagram
(AVDD=TVDD=3.3V, VDDL/R=5.0V, LDOE= “L”, Register Control Mode)
Rev. 0.1
- 91 -
2015/11