AK4497 Datasheet, PDF (68/98 Pages) Asahi Kasei Microsystems – Quality Oriented 32-Bit 2ch DAC

[AK4497]
(b) Register Control Mode (PSN pin= “L”)
A register access becomes available after the PDN pin = “H”. The analog circuit starts operation by
supplying necessary clocks (MCLK, LRCK and BICK for PCM mode, MCLK and DCLK for DSD mode,
MCLK, BCK and WCK for EXDF mode) and the clock divider is powered up about after 4/fs. The
analog output pins output analog common voltages (VCML, VCMR) in this time. Then the AK4497
transitions to normal operation by setting RSTN bit = “1”. When power up the AK4497 with the LDOE
pin = “H”, 3.3V power supplies (AVDD and TVDD) should be powered up before or at the same time of
5V power supplies (VDDL/R and VREFHL/R).
Power
(TVDD,AVDD)
Power
（VDDL/R,VREFHL/R）
PDN pin
(1)
DVDD pin
Internal PDN
(2)
RSTN bit
Internal State
(Resister
(Clock devider)
(8)
Power Off
(9)
Internal State
(Digital Core)
Power Off
DAC In
(Digital)
DAC Out
(Analog)
(4)
(5)
Clock In
Don’t care
MCLK,LRCK,BICK
Normal Operation
Normal Operation
“0”data
GD ⁽³⁾
Power Off
(9)
Power Off
“0”data
GD
(5)
(4)
Don’t care
DZFL/R
(7)
Figure 52. Power-down/up Sequence Example (Resister Control Mode, LDOE pin= “H”)
Notes:
(1) The PDN pin must be held “L” for more than 150ns after supplying AVDD, TVDD and VDDL/R.
(2) Internal LDO is powered up after the PDN pin = “H” when the LDOE pin= “H”. The internal circuit
will starts operation after the shutdown switch is ON (max. 2ms) following the internal oscillator
count up.
(3) The analog output corresponding to the digital input has group delay (GD).
(4) Analog outputs are floating (Hi-Z) in power down mode.
(5) Click noise occurs at the edge of PDN signal. This noise is output even if “0” data is input.
(6) Mute the analog output externally if click noise (5) adversely affect system performance.
(7) The DZFL/R pins are “L” in power-down mode (PDN pin = “L”).
(8) The clock divider is powered up in about 4/fs after the internal PDN is released.
Rev. 0.1
- 68 -
2015/11