AK4497 Datasheet, PDF (74/98 Pages) Asahi Kasei Microsystems – Quality Oriented 32-Bit 2ch DAC

[AK4497]
If RSTN bit is set to “0”, the output signal of the DZFL/DZFR pin becomes “H”. Then, the DAC is reset 3 to
4/fs after the DZFL and the DZFR pins = “H” and the analog output becomes the same voltage as
VCML/R. The synchronize function becomes valid when both of the DZFL and the DZFR pins output “H”.
RSTN bit
Internal
RSTN bit
3~4/fs (4)
2~3/fs (4)
Internal
State
D/A In
(Digital)
D/A Out
(Analog)
Normal Operation
(3)
GD
Both DZFL/R pin
Internal Counter
Reset
Internal
Data
Digital Block Power-down
Normal Operation
force”0” (2)
(5)
(5)
SYNC Operation (1)
2/fs(4)
GD (3)
2~3/fs (2)
Note:
(1) The DZFL and the DZFR pins become “H” by a falling edge of RSTN bit, and becomes “L” 2/fs after a
rising edge of internal signal of RSTN bit. The synchronize function is valid During the DZFL/R pin =
“H”.
(2) Internal data is fixed to “0” forcibly for 2 to 3/fs when the internal counter is reset.
(3) Since the analog output corresponding to digital input has group delay (GD), it is recommended to
have a no-input period longer than the group delay before writing “0” to RSTN bit.
(4) It takes 3 to 4/fs when falling to change the internal RSTN signal of the LSI after writing to RSTN bit. It
also takes 2 to 3/fs when rising to change the internal RSTN signal of the LSI. The synchronize
function becomes valid immediately when “0” is written to RSTN bit. Therefore, there is a case that the
internal counter is reset before internal RSTN signal of the LSI is changed.
(5) A click noise occurs on the rising or falling edge of the internal RSTN signal and when the internal
counter is reset. This noise is output even if a “0” data is input. Mute the analog output externally if this
click noise affects the system performance.
Figure 58. Synchronizing Sequence by RSTN Bit
Rev. 0.1
- 74 -
2015/11