AK4497 Datasheet, PDF (38/98 Pages) Asahi Kasei Microsystems – Quality Oriented 32-Bit 2ch DAC

[AK4497]
(1) Pin Control Mode (PSN pin = “H”)
1-1. Manual Setting Mode (ACKS pin = “L”)
The MCLK frequency corresponding to each sampling speed should be provided externally (Table 6).
DFS1-0 bit is fixed to “00”. In this mode, quad speed and double speed modes are not available.
Table 6. System Clock Example (Manual Setting Mode @Pin Control Mode)(N/A: Not available)
LRCK
MCLK (MHz)
BICK
fs
128fs
192fs
256fs
384fs
512fs
768fs 1152fs
64fs
32.0kHz N/A
N/A
8.1920 12.2880 16.3840 24.5760 36.8640 2.0480MHz
44.1kHz N/A
N/A 11.2896 16.9344 22.5792 33.8688 N/A 2.8224MHz
48.0kHz N/A
N/A 12.2880 18.4320 24.5760 36.8640 N/A 3.0720MHz
1-2. Auto Setting Mode (ACKS pin = “H”)
In auto setting mode, MCLK frequency and sampling frequency are detected automatically (Table 7).
MCLK of corresponded frequency to each sampling speed mode should be input externally (Table 8).
Table 7. Sampling Speed (Auto Setting Mode @Pin Control Mode)
MCLK
Sampling Speed
1152fs
Normal (fs32kHz)
512fs/256fs 768fs/384fs
Normal
256fs
384fs
Double
128fs
192fs
Quad
64fs
96fs
Oct
32fs
48fs
Hex
LRCK
fs
32.0kHz
44.1kHz
48.0kHz
88.2kHz
96.0kHz
176.4kHz
192.0kHz
384kHz
768kHz
Table 8. System Clock Example (Auto Setting Mode @Pin Control Mode) (N/A: Not available)
MCLK(MHz)
Sampling
32fs 48fs 64fs 96fs 128fs 192fs 256fs 384fs 512fs 768fs 1024fs 1152fs Speed
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A 8.1920 12.2880 16.3840 24.5760 32.7680 36.8640
N/A 11.2896 16.9344 22.5792 33.8688 N/A
N/A
Normal
N/A 12.2880 18.4320 24.5760 36.8640 N/A
N/A
N/A 22.5792 33.8688 N/A
N/A 24.5760 36.8640 N/A
N/A
N/A
N/A
N/A
N/A
N/A
Double
N/A
N/A
N/A
N/A 22.5792 33.8688 N/A
N/A
N/A
N/A
N/A
N/A
Quad
N/A
N/A
N/A
N/A 24.5760 36.8640 N/A
N/A
N/A
N/A
N/A
N/A
Quad
N/A
N/A 24.576 36.864 N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Oct
24.576 36.864 N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Hex
When MCLK= 256fs/384fs, auto setting mode supports sampling rate of 8kHz~96kHz (Table 9).
However, the DR and S/N performances will degrade approximately 3dB as compared to when MCLK =
256fs/384fs for DR and MCLK= 512fs/768fs for S/N, respectively if the sampling rate is under 54kHz.
Table 9. DR and S/N Relationship with MCLK Frequency (fs = 44.1kHz)
ACKS pin
MCLK
DR,S/N
L
256fs/384fs/512fs/768fs
127dB
H
256fs/384fs
124dB
H
512fs/768fs
127dB
Rev. 0.1
- 38 -
2015/11