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AK4497 Datasheet, PDF (6/98 Pages) Asahi Kasei Microsystems – Quality Oriented 32-Bit 2ch DAC | |||
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â Pin Functions
[AK4497]
No. Pin Name I/O
Function
1 LDOE
I Internal LDO Enable Pin. âLâ: Disable, âHâ: Enable
2 PDN
Power-Down Mode Pin
I When at âLâ, the AK4497 is in power-down mode and is held in reset. The
AK4497 must always be reset upon power-up.
BICK
I Audio Serial Data Clock Pin in PCM Mode
3 BCK
I Audio Serial Data Clock Pin
DCLK
I DSD Clock Pin in DSD Mode (DSDPATH bit = â1â)
SDATA
I Audio Serial Data Input Pin in PCM Mode
4 DINL
I Lch Audio Serial Data Input Pin
DSDL
I DSD Lch Data Input Pin in DSD Mode(DSDPATH bit = â1â)
LRCK
I L/R Clock Pin in PCM Mode
5 DINR
DSDR
I Rch Audio Serial Data Input Pin
I DSD Rch Data Input Pin in DSD Mode(DSDPATH bit = â1â)
SSLOW
6 WCK
I Digital Filter Select Pin in Parallel Control Mode
I Word Clock input pin
7 TDMO
O Audio Serial Data Onput in Daisy Chain mode (Internal pull-down pin)
SMUTE
8
I When this pin is changed to âHâ, soft mute cycle is initiated.
When returning âLâ, the output mute releases.
CSN
I Chip Select Pin in Serial Control Mode
SD
I Digital Filter Select Pin in Parallel Control Mode
9 CCLK
I Control Data Clock Pin in Serial Control Mode
SCL
I I2C=âHâ: Control Data Clock Input Pin
SLOW
I Digital Filter Select Pin in Parallel Control Mode
10 CDTI
I Control Data Input Pin in Serial Control Mode
SDA
I/O I2C=âHâ: Control Data Input Pin
DIF0
11
DZFL
I Digital Input Format 0 Pin in Parallel Control Mode
O Lch Zero Input Detect Pin in Serial Control Mode (Internal pull-down pin)
DIF1
12
DZFR
I Digital Input Format 1 Pin in Parallel Control Mode
O Rch Zero Input Detect Pin in Serial Control Mode (Internal pull-down pin)
DIF2
13
CAD0
I Digital Input Format 2 Pin in Parallel Control Mode
I Chip Address 0 Pin in Serial Control Mode
14 PSN
I
Parallel or Serial Select Pin
(Internal pull-up pin)
âLâ: Serial Control Mode, âHâ: Parallel Control Mode
HLOAD
15
I2C
I Heavy Load Mode Enable Pin in Parallel Control Mode.
Resister Control Interface Pin in Serial Control Mode.
DEM0
16
DSDL
I De-emphasis Enable 0 Pin in Parallel Control Mode
I DSD Lch Data Input Pin in DSD Mode (DSDPATH bit =â0â)
GAIN
17
DSDR
ACKS
18
CAD1
I Output Gain Control Pin in Parallel control mode (+2.5dB)
I DSD Rch Input Pin in DSD Mode (DSDPATH bit =â0â)
I
Auto Setting Mode Select Pin in Parallel control mode
âLâ: Manual Setting Mode, âHâ: Auto Setting Mode
I Chip Address 1 Pin in Serial Control Mode
Rev. 0.1
2015/11
-6-
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