AK4497 Datasheet, PDF (66/98 Pages) Asahi Kasei Microsystems – Quality Oriented 32-Bit 2ch DAC

[AK4497]
■ Power Up/Down Function
The AK4497 is powered down by setting the PDN pin to “L”. In power-down state, all circuits stop
operation and initialized, and the analog output becomes floating (Hi-z) state. The PDN pin must held “L”
for more than 150ns for a certain reset. There is a possibility of malfunctions with the “L” pulse less than
150ns. Power-down is released by setting the PDN pin to “H” from “L”. In this time IREF and LDO (if
LDOE pin = “H”) are powered up and the analog output becomes floating (Hi-z) state.
(a) Pin Control Mode (PSN pin = “H”)
All circuits will be powered up by inputting MCLK, LRCK and BICK clocks after the PDN pin = “H”. The
analog circuit starts operation just after supplying all necessary clocks (MCLK, LRCK and BICK) and the
digital circuit starts operation about 4/fs after the clock supply. Figure 50 shows system timing example of
power down/up when using the internal LDO (LDOE pin “H”). When power up the AK4497 with the LDOE
pin = “H”, 3.3V power supplies (AVDD and TVDD) should be powered up before or at the same time of 5V
power supplies (VDDL/R and VREFHL/R).
Power
(TVDD,AVDD)
Power
（VDDL/R,VREFHL/R）
PDN pin
(1)
DVDD pin
Internal PDN
(2)
Internal
State
DAC In
(Digital)
DAC Out
(Analog)
(4)
(5)
Clock In
Don’t care
MCLK,LRCK,BICK
External
Mute
(6)
Normal Operation (DAC Input Available)
Reset
“0”data
GD ⁽³⁾
“0”data
GD
(5)
(4)
Don’t care
Mute ON
Mute ON
Figure 50. Power-down/up Sequence Example (Pin Control Mode, LDOE pin= “H”)
Notes:
(1) The PDN pin must be held “L” for more than 150ns after supplying AVDD, TVDD and VDDL/R.
(2) Internal LDO is powered up after the PDN pin = “H” when the LDOE pin= “H”. The internal circuit
will starts operation after the shutdown switch is ON (max. 2ms) following the internal oscillator
count up.
(3) The analog output corresponding to the digital input has group delay (GD).
(4) Analog outputs are floating (Hi-Z) in power down mode.
(5) Click noise occurs at the edge of PDN signal. This noise is output even if “0” data is input.
(6) Mute the analog output externally if click noise (5) adversely affect system performance. The
timing example when not using LDO (LODE pin = “L”) is shown in Figure 51. When the LDOE
pin= “L”, 1.8V (DVDD), 3.3V (AVDD, TVDD) and 5V (VDDL, VDDR, VREFHL, VREFHR) power
supplies should be powered up at the same time, otherwise power up the 3.3V power supplies
Rev. 0.1
- 66 -
2015/11